32 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF032B
Data Sheet
SST's 25 series Serial Flash family features a four-wire, SPI-compatible inter-
face that allows for a low pin-count package which occupies less board space
and ultimately lowers total system costs. The SST25VF032B devices are
enhanced with improved operating frequency which lowers power consumption.
SST25VF032B SPI serial flash memories are manufactured with SST's proprie-
tary, high-performance CMOS SuperFlash technology. The split-gate cell design
and thick-oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches.
Features:
• Single Voltage Read and Write Operations
– 2.7-3.6V
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• High Speed Clock Frequency
– Up to 80 MHz
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Low Power Consumption:
– Active Read Current: 10 mA (typical)
– Standby Current: 5 µA (typical)
• Temperature Range
– Industrial: -40°C to +85°C
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Packages Available
– 8-lead SOIC (200 mils)
– 8-contact WSON (5 X 6 mm)
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 µs (typical)
• All devices are RoHS compliant
• Auto Address Increment (AAI) Word Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
©2011 Silicon Storage Technology, Inc.
www.microchip.com
www.sst.com
S71327-04-000
02/11
32 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF032B
Data Sheet
Product Description
The SST 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for
a low pin-count package which occupies less board space and ultimately lowers total system
costs. SST25VF032B SPI serial flash memories are manufactured with SST’s proprietary, high-
performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability compared with alternate approaches.
The SST25VF032B devices significantly improve performance and reliability, while lowering power
consumption. The devices write (Program or Erase) with a single power supply of 2.7-3.6V for
SST25VF032B. The total energy consumed is a function of the applied voltage, current, and time
of application. Since for any given voltage range, the SuperFlash technology uses less current to
program and has a shorter erase time, the total energy consumed during any Erase or Program
operation is less than alternative flash memory technologies.
The SST25VF032B device is offered in 8-lead SOIC (200 mils) and 8-contact WSON packages.
See Figure 2 for pin assignments.
©2011 Silicon Storage Technology, Inc.
S71327-04-000
02/11
2
32 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF032B
Data Sheet
Block Diagram
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CE#
SCK
SI
SO
WP#
HOLD#
1327 B1.0
Note:
In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of-Write
Detection” on page 12. for details
Figure 1:
Functional Block Diagram
©2011 Silicon Storage Technology, Inc.
S71327-04-000
02/11
3
32 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF032B
Data Sheet
Pin Description
CE#
SO
WP#
V
SS
1
2
Top View
3
4
8
7
6
5
V
DD
HOLD#
SCK
SI
CE#
SO
WP#
V
SS
1
8
V
DD
HOLD#
SCK
SI
2
7
Top View
3
6
4
5
1327 8-SOIC P1.0
1327 8-WSON P1.0
Note:
In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of-Write
Detection” on page 12. for details.
Figure 2:
Pin Assignments for 8-Lead SOIC
Table 1:
Pin Description
Symbol
SCK
Pin Name
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SI
SO
RY/BY#
CE#
WP#
HOLD#
V
DD
V
SS
Serial Data Input
Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Ready / Busy pin
Chip Enable
Write Protect
Hold
Power Supply
Ground
T1.0 1327
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY#
pin.
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status reg-
ister.
To temporarily stop serial communication with SPI flash memory without reset-
ting the device.
To provide power supply voltage: 2.7-3.6V
©2011 Silicon Storage Technology, Inc.
S71327-04-000
02/11
4
32 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF032B
Data Sheet
Memory Organization
The SST25VF032B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable blocks.
Device Operation
The SST25VF032B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF032B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1327 F04.0
HIGH IMPEDANCE
Figure 3:
SPI Protocol
©2011 Silicon Storage Technology, Inc.
S71327-04-000
02/11
5
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