2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
The 25 series Serial Flash family features a four-wire, SPI compatible interface
that allows for a low pin-count package which occupies less board space and ulti-
mately lowers total system costs. The SST25VF020B devices are enhanced with
improved operating frequency and even lower power consumption.
SST25VF020B SPI serial flash memories are manufactured with SST proprietary,
high performance CMOS SuperFlash technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and manufacturability com-
pared with alternate approaches.
Features
• Single Voltage Read and Write Operations
– 2.7-3.6V
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin in AAI Mode
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• High Speed Clock Frequency
– Up to 80 MHz
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Superior Reliability
– Endurance: 100,000 Cycles
– Greater than 100 years Data Retention
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Low Power Consumption:
– Active Read Current: 10 mA (typical)
– Standby Current: 5 µA (typical)
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Packages Available
– 8-lead SOIC (150 mils)
– 8-contact WSON (6mm x 5mm)
– 8-contact USON (3mm x 2mm)
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 µs (typical)
• All non-Pb (lead-free) devices are RoHS compliant
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
©2013 Silicon Storage Technology, Inc.
www.microchip.com
DS20005054C
04/13
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Product Description
The 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for a low
pin-count package which occupies less board space and ultimately lowers total system costs. The
SST25VF020B devices are enhanced with improved operating frequency and even lower power con-
sumption. SST25VF020B SPI serial flash memories are manufactured with SST proprietary, high-per-
formance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with alternate approaches.
The SST25VF020B devices significantly improve performance and reliability, while lowering power
consumption. The devices write (Program or Erase) with a single power supply of 2.7-3.6V for
SST25VF020B. The total energy consumed is a function of the applied voltage, current, and time of
application. Since for any given voltage range, the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy consumed during any Erase or Program operation
is less than alternative flash memory technologies.
The SST25VF020B device is offered in 8-lead SOIC (150 mils) 8-contact WSON (6mm x 5mm), and 8-
contact USON (3mm x 2mm) packages. See Figure 2 for pin assignments.
©2013 Silicon Storage Technology, Inc.
DS20005054C
04/13
2
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Functional Block Diagram
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CE#
SCK
SI
SO
WP#
HOLD#
1417 B1.0
Figure 1:
Functional Block Diagram
©2013 Silicon Storage Technology, Inc.
DS20005054C
04/13
3
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Pin Description
CE#
SO
WP#
VSS
1
2
8
7
VDD
HOLD#
SCK
SI
CE#
SO
WP#
VSS
1
8
VDD
HOLD#
SCK
SI
2
7
Top View
3
4
6
5
3
Top View
6
4
5
8-Lead SOIC
1417 08-soic S2A P1.0
8-Contact WSON
1417 08-wson QA P2.0
CE#
SO
WP#
VSS
1
8
VDD
HOLD#
SCK
SI
2
Top View
7
3
6
4
5
8-Contact USON
1417 08-uson Q3A P1.0
Figure 2:
Pin Assignments
Table 1:
Pin Description
Symbol
SCK
Pin Name
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SI
SO
Serial Data Input
Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/
BY# pin. See “Hardware End-of-Write Detection” on page 14 for details.
Chip Enable
Write Protect
Hold
Power Supply
Ground
T1.0 25054
CE#
WP#
HOLD#
V
DD
V
SS
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status reg-
ister.
To temporarily stop serial communication with SPI flash memory without reset-
ting the device.
To provide power supply voltage: 2.7-3.6V for SST25VF020B
©2013 Silicon Storage Technology, Inc.
DS20005054C
04/13
4
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Memory Organization
The SST25VF020B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable blocks.
Device Operation
The SST25VF020B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF020B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1417 SPIprot.0
HIGH IMPEDANCE
Figure 3:
SPI Protocol
©2013 Silicon Storage Technology, Inc.
DS20005054C
04/13
5
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