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74AUP2G07FW3-7

产品描述AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6
产品类别半导体    逻辑   
文件大小450KB,共13页
制造商Diodes
官网地址http://www.diodes.com/
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74AUP2G07FW3-7概述

AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6

AUP/ULP/V 系列, 双 1输入 同相门, PDSO6

74AUP2G07FW3-7规格参数

参数名称属性值
功能数量2
端子数量6
最大工作温度125 Cel
最小工作温度-40 Cel
最大供电/工作电压3.6 V
最小供电/工作电压0.8000 V
额定供电电压3 V
加工封装描述1 X 1 MM, GREEN, DFN-6
状态ACTIVE
工艺CMOS
包装形状SQUARE
包装尺寸SMALL OUTLINE, VERY THIN PROFILE
表面贴装Yes
端子形式NO LEAD
端子间距0.3500 mm
端子位置DUAL
包装材料PLASTIC/EPOXY
温度等级AUTOMOTIVE
系列AUP/ULP/V
输出特性O-DRN
逻辑IC类型NON-INVERT
输入数1
传播延迟TPD25.8 ns

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74AUP2G07
DUAL BUFFERS WITH OPEN DRAIN OUTPUTS
Description
The Advanced Ultra Low Power (AUP) CMOS logic family is designed
for low power and extended battery life in portable applications.
The 74AUP2G07 is composed of two buffers with open drain outputs
designed for operation over a power supply range of 0.8V to 3.6V.
The device is fully specified for partial power down applications using
I
OFF
. The I
OFF
circuitry disables the output preventing damaging
Pin Assignments
(Top View)
1A
1
GND
2
2A
3
SOT363
6
1Y
5
Vcc
4
2Y
(Top View)
1A
GND
2A
1
2
3
6
1Y
5
Vcc
4
2Y
NEW PRODUCT
current backflow when the device is powered down. The gates
perform the positive Boolean function:
Y
½
A
X2-DFN1410-6
Features
Advanced Ultra Low Power (AUP) CMOS
Supply Voltage Range from 0.8V to 3.6V
-4mA Output Drive at 3.0V
Low Static Power Consumption
I
CC
< 0.9µA
Low Dynamic Power Consumption
C
PD
= 1.2pF Typical at 3.6V
Schmitt Trigger Action at All Inputs Make the Circuit Tolerant for
Slower Input Rise and Fall Time. The Hysteresis is Typically
250mV at V
CC
= 3.0V
I
OFF
Supports Partial-Power-Down Mode Operation
ESD Protection per JESD 22
Exceeds 200-V Machine Model (A115)
Exceeds 2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
Latch-Up Exceeds 100mA per JESD 78, Class I
Leadless Packages per JESD30E
DFN1410 denoted as X2-DFN1410-6
DFN1010 denoted as X2-DFN1010-6
DFN0910 denoted as X2-DFN0910-6
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
(Top View)
1A
GND
2A
1
2
3
6
5
4
1Y
Vcc
2Y
(Top View)
1A
GND
2A
1
2
3
5
4
1Y
Vcc
2Y
X2-DFN1010-6
X2-DFN0910-6
Applications
Suited for Battery and Low Power Needs
Wide array of products such as:
PCs, Networking, Notebooks, Netbooks, PDAs
Tablet Computers, E-readers
Computer Peripherals, Hard Drives, CD/DVD ROM
TV, DVD, DVR, Set-Top Box
Cell Phones, Personal Navigation / GPS
MP3 players, Cameras, Video Recorders
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
74AUP2G07
Document number: DS35511 Rev. 5 - 2
1 of 13
www.diodes.com
November 2014
© Diodes Incorporated

74AUP2G07FW3-7相似产品对比

74AUP2G07FW3-7 74AUP2G07FW4-7 74AUP2G07
描述 AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6 AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6 AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6
功能数量 2 2 2
端子数量 6 6 6
最大工作温度 125 Cel 125 Cel 125 Cel
最小工作温度 -40 Cel -40 Cel -40 Cel
最大供电/工作电压 3.6 V 3.6 V 3.6 V
最小供电/工作电压 0.8000 V 0.8000 V 0.8000 V
额定供电电压 3 V 3 V 3 V
加工封装描述 1 X 1 MM, GREEN, DFN-6 1 X 1 MM, GREEN, DFN-6 1 X 1 MM, GREEN, DFN-6
状态 ACTIVE ACTIVE ACTIVE
工艺 CMOS CMOS CMOS
包装形状 SQUARE SQUARE SQUARE
包装尺寸 SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE
表面贴装 Yes Yes Yes
端子形式 NO LEAD NO LEAD NO LEAD
端子间距 0.3500 mm 0.3500 mm 0.3500 mm
端子位置 DUAL DUAL DUAL
包装材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
温度等级 AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
系列 AUP/ULP/V AUP/ULP/V AUP/ULP/V
输出特性 O-DRN O-DRN O-DRN
逻辑IC类型 NON-INVERT NON-INVERT NON-INVERT
输入数 1 1 1
传播延迟TPD 25.8 ns 25.8 ns 25.8 ns
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