SM803020
Flexible Ultra-Low Jitter Clock Synthesizer
General Description
The SM803020 is a dual-PLL clock generator that
achieves ultra-low, 74.2fs_rms output jitter at 156.25MHz
output frequency. It accepts a crystal input or a reference
input.
Each output channel is individually configurable to a
differential PECL, LVDS, HCSL, or CMOS output logic
level. PECL is selected by default, but can be overridden
through SPI. It is packaged in a dual-row 84-pin
7mm x 7mm package.
Datasheets and support documentation are available on
Micrel’s web site at:
www.micrel.com.
Features
•
Generates twelve 156.25MHz outputs
•
Independently programmable output logic:
−
Output logic: LVPECL (default), LVDS, HCSL,
LVCMOS
•
74.2fs jitter at 156.25MHz (1.875MHz to 20MHz)
•
Selectable inputs require 39.0625MHz input frequency
−
XTAL (default)
−
Differential or single-ended reference clock (SPI
selectable)
•
2.5V or 3.3V operating power supply
•
Separate output power supplies:
−
Different banks can be at different levels
•
Industrial temperature range (–40°C to +85°C)
•
Green, RoHS, and PFOS compliant
•
Available in 84-pin 7mm
×
7mm QFN package
Typical Application
Applications
•
1/10/40/100 Gigabit Ethernet
Micrel Inc. • 2180 Fortune Drive •
San
Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
July 22, 2013
Revision 1.0
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SM803020
Ordering Information
Part Number
SM803020UMY
SM803020UMYR
Marking
803020
803020
Shipping
Tray
Tape and Reel
Ambient Temperature Range
–40°C to +85°C
–40°C to +85°C
Package
84-Pin QFN
84-Pin QFN
Pin Configuration
84-Pin
QFN
7mm x 7mm
July 22, 2013
2
Revision 1.0
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SM803020
Pin Description
Pin Number
A19, A20
A17, A18
A15, A16
A13, A14
A10, A11
A8, A9
A36, A37
A38, A39
A40, A41
A42, A43
A1, A2
A3, A4
B12
B11
B40
A44
A21, A35
B18
B17
B8
B9
B33
B37
B2
B3
B20
B31
A27, B25
A28
B30
B36
B15
B16
B10
B13
Pin Name
QA1, /QA1
QA2, /QA2
QA3, /QA3
QB1, /QB1
QB2, /QB2
QB3, /QB3
QC1, /QC1
QC2, /QC2
QC3, /QC3
QD1, /QD1
QD2, /QD2
QD3, /QD3
FSEL_A
FSEL_B
FSEL_C
FSEL_D
VDD
VDDOA1
VDDOA2
VDDOA3
VDDOB1
VDDOB2
VDDOB3
VDDOC1
VDDOC2
VDDOC3
VDDOD1
VDDOD2
VDDOD3
VDDAP1
VDDAP2
VDDI1
VDDI2
VSS
(Exposed Pad)
VSSOA1
VSSOA2
VSSOA3
VSSOB1
VSSOB2
VSSOB3
Pin Type
Pin Level
Pin Function
O, (DIF/SE)
LVPECL
Differential LVPECL (default), HCSL, or LVDS Clock
Outputs or Phase-Adjustable Differential or Single-Ended
CMOS Outputs
I, (SE)
LVCMOS
Frequency Select, 75kΩ
pull-up
1 = Primary Selection
0 = Secondary Selection
Power Supply
Power Supply for Outputs QA1−3
PWR
PWR
PWR
Power Supply for Outputs QB1−3
PWR
Power Supply for Outputs QC1−3
PWR
PWR
PWR
PWR
PWR
PWR
3.3V only
Power Supply for Outputs QD1−3
Power Supply for PLL1
Power Supply for PLL2
Power Supply for VCXO, Reference1, Feedback 1
Power Supply for XO, Reference2, Feedback 2
Core Power Supply Ground. The exposed pad must be
connected to the VSS ground plane.
Power Supply Ground for Outputs QA1−3
PWR
PWR
Power Supply Ground for Outputs QB1−3
July 22, 2013
3
Revision 1.0
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
Pin Number
B34
B35
B4
B39
A34
A22
A23
A31
B14
A12
B38
B1
A5, A6, A7,
B5, B6, B7
A32
A33
Pin Name
VSSOC1
VSSOC2
VSSOC3
VSSOD1
VSSOD2
VSSOD3
VSSAP1
VSSAP2
VSSI1
VSSI2
OEA1/2/3
OEB1/2/3
OEC1/2/3
OED1/2/3
TEST
Pin Type
PWR
Pin Level
Pin Function
Power Supply Ground for Outputs QC1−3
SM803020
PWR
PWR
PWR
PWR
PWR
I, (SE)
I, (SE)
I, (SE)
I, (SE)
-
LVCMOS
LVCMOS
LVCMOS
LVCMOS
-
LVPECL
LVDS
HCSL
LVCMOS
LVPECL
LVDS
HCSL
LVCMOS
LVPECL
LVDS
HCSL
LVCMOS
LVPECL
LVDS
HCSL
LVCMOS
LVPECL
LVDS
HCSL
LVCMOS
12pF crystal
12pF crystal
Power Supply Ground for Outputs QD1−3
Power Supply Ground for PLL1
Power Supply Ground for PLL2
Power Supply Ground for VCXO, Reference1, Feedback 1
Power Supply Ground for XO, Reference2, Feedback 2
Output Enable, Outputs Q0–Q3 disable to tri-state,
0 = Disabled, 1 = Enabled, 75kΩ
pull-up
Output Enable, Outputs Q4–Q7 disable to tri-state,
0 = Disabled, 1 = Enabled, 75kΩ
pull-up
Output Enable, Outputs Q4–Q7 disable to tri-state,
0 = Disabled, 1 = Enabled, 75kΩ
pull-up
Output Enable, Outputs Q4–Q7 disable to tri-state,
0 = Disabled, 1 = Enabled, 75kΩ
pull-up
Factory Test pins. Do not connect anything to these pins.
REFOUT_P,
REFOUT_N
I, (Diff/SE)
Reference Clock Output
B21
B22
REF1_P, REF1_N
I, (Diff/SE)
Reference Clock Input 1
B28
B29
REF2_P, REF2_N
I, (Diff/SE)
Reference Clock Input2
B23
B24
FB1_P, FB1_N
I, (Diff/SE)
Feedback Clock Input1
B26
B27
FB2_P, FB2_N
I, (Diff/SE)
Feedback Clock Input2
A29
A30
XTAL_IN
XTAL_OUT
I, (SE)
O, (SE)
Crystal Reference Input, no load caps needed
(See
Figure 9.)
Crystal Reference Output, no load caps needed
(See
Figure 9.)
July 22, 2013
4
Revision 1.0
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
Pin Number
B19, B32
A25
A26
A24
Pin Name
NC
VCXO_OUT
VCXO_IN
VC
O, SE
I, SE
I
VCXO output, 8 to 10pF, programmable
VCXO input, 8 to 10pF, programmable
Control voltage for VCXO, positive slope
Pin Type
Pin Level
Pin Function
SM803020
Truth Tables
PLL_BYPASS
0
1
−
−
−
−
−
−
FSEL
1
0
XTAL_SEL
−
−
0
1
−
−
−
−
OEA
1
1
1
1
0
1
1
1
OEB
1
1
1
1
1
0
1
1
OEC
1
1
1
1
1
1
0
1
OED
1
1
1
1
1
1
1
0
Input
−
−
REF_IN
XTAL
−
−
−
−
Output
PLL
XTAL/REF_IN
−
−
QA Tri-state
QB Tri-state
QC Tri-state
QD Tri-state
Output Frequency (MHz)
Primary
Secondary
Output
Logic Programming
Available output logic types are LVPECL (default), LVDS,
HCSL and LVCMOS.
Each output can be programmed individually to any of the
four logic types through SPI.
Unused outputs can be disabled to high impedance.
All logic types are differential except LVCMOS. LVCMOS
signals are single ended coming out of the Qx pins. During
LVCMOS operation the /Qx pins are disabled.
July 22, 2013
5
Revision 1.0
hbwhelp@micrel.com
or (408) 955-1690
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
