converters designed for digitizing high frequency, wide
dynamic range signals. They are perfect for demanding
communications applications with AC performance that
includes 77dB SNR and 90dB spurious free dynamic range
(SFDR). Ultralow jitter of 0.07ps
RMS
allows undersampling
of IF frequencies with excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.3LSB
RMS
.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
+
and ENC
–
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
77dB SNR
90dB SFDR
Low Power: 87mW/63mW/45mW
Single 1.8V Supply
CMOS, DDR CMOS, or DDR LVDS Outputs
Selectable Input Ranges: 1V
P-P
to 2V
P-P
550MHz Full Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
48-Pin (7mm
×
7mm) QFN Package
applicaTions
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
Typical applicaTion
1.8V
V
DD
1.8V
OV
DD
2-Tone FFT, f
IN
= 70MHz and 69MHz
0
–10
–20
–30
AMPLITUDE (dBFS)
D15
•
•
•
D0
–40
–50
–60
–70
–80
ANALOG
INPUT
S/H
16-BIT
ADC CORE
OUTPUT
DRIVERS
CMOS
DDR CMOS OR
DDR LVDS
OUTPUTS
125MHz
CLOCK
CLOCK
CONTROL
–90
–100
–110
–120
OGND
0
216210 TA01a
GND
20
10
FREQUENCY (MHz)
30
2162 TA01b
216210f
1
LTC2162/LTC2161/LTC2160
absoluTe MaxiMuM raTings
(Notes 1, 2)
Supply Voltages (V
DD
, O
VDD
) ....................... –0.3V to 2V
Analog Input Voltage (A
IN+
, A
IN –
, PAR/SER, SENSE)
(Note 3) ................................... –0.3V to (V
DD
+ 0.2V)
Digital Input Voltage (ENC
+
, ENC
–
,
CS,
SDI, SCK)
(Note 4) ................................................ –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage ................–0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range
LTC2162C, LTC2161C, LTC2160C............. 0°C to 70°C
LTC2162I, LTC2161I, LTC2160I ............–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
pin conFiguraTion
FULL RATE CMOS OUTPUT MODE
TOP VIEW
48 V
DD
47 V
DD
46 SENSE
45 V
REF
44 SDO
43 GND
42 OF
41 DNC
40 D15
39 D14
38 D13
37 D12
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
48 V
DD
47 V
DD
46 SENSE
45 V
REF
44 SDO
43 GND
42 OF
41 DNC
40 D14_15
39 DNC
38 D12_13
37 DNC
36 D11
35 D10
34 D9
33 D8
32 OV
DD
31 OGND
30 CLKOUT
+
29 CLKOUT
–
28 D7
27 D6
26 D5
25 D4
V
CM
1
A
IN +
2
A
IN –
3
GND 4
REFH 5
REFL 6
REFH 7
REFL 8
PAR/SER 9
GND 10
GND 11
V
DD
12
49
GND
36 D10_11
35 DNC
34 D8_9
33 DNC
32 OV
DD
31 OGND
30 CLKOUT
+
29 CLKOUT
–
28 D6_7
27 DNC
26 D4_5
25 DNC
UK PACKAGE
48-LEAD (7mm
×
7mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 29°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
V
DD
13
GND 14
ENC
+
15
ENC
–
16
CS
17
SCK 18
SDI 19
GND 20
DNC 21
D0_1 22
DNC 23
D2_3 24
V
CM
1
A
IN +
2
A
IN –
3
GND 4
REFH 5
REFL 6
REFH 7
REFL 8
PAR/SER 9
GND 10
GND 11
V
DD
12
49
GND
UK PACKAGE
48-LEAD (7mm
×
7mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 29°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
V
DD
13
GND 14
ENC
+
15
ENC
–
16
CS
17
SCK 18
SDI 19
GND 20
D0 21
D1 22
D2 23
D3 24
216210f
2
LTC2162/LTC2161/LTC2160
pin conFiguraTion
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
48 V
DD
47 V
DD
46 SENSE
45 V
REF
44 SDO
43 GND
42 OF
+
41 OF
–
40 D14_15
+
39 D14_15
–
38 D12_13
+
37 D12_13
–
V
CM
1
A
IN +
2
A
IN –
3
GND 4
REFH 5
REFL 6
REFH 7
REFL 8
PAR/SER 9
GND 10
GND 11
V
DD
12
49
GND
36 D10_11
+
35 D10_11
–
34 D8_9
+
33 D8_9
–
32 OV
DD
31 OGND
30 CLKOUT
+
29 CLKOUT
–
28 D6_7
+
27 D6_7–
26 D4_5
+
25 D4_5–
UK PACKAGE
48-LEAD (7mm
×
7mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 29°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC2162CUK#PBF
LTC2162IUK#PBF
LTC2161CUK#PBF
LTC2161IUK#PBF
LTC2160CUK#PBF
LTC2160IUK#PBF
TAPE AND REEL
LTC2162CUK#TRPBF
LTC2162IUK#TRPBF
LTC2161CUK#TRPBF
LTC2161IUK#TRPBF
LTC2160CUK#TRPBF
LTC2160IUK#TRPBF
PART MARKING*
LTC2162UK
LTC2162UK
LTC2161UK
LTC2161UK
LTC2160UK
LTC2160UK
PACKAGE DESCRIPTION
48-Lead (7mm
×
7mm) Plastic QFN
48-Lead (7mm
×
7mm) Plastic QFN
48-Lead (7mm
×
7mm) Plastic QFN
48-Lead (7mm
×
7mm) Plastic QFN
48-Lead (7mm
×
7mm) Plastic QFN
48-Lead (7mm
×
7mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
V
DD
13
GND 14
ENC
+
15
ENC
–
16
CS
17
SCK 18
SDI 19
GND 20
D0_1
–
21
D0_1
+
22
D2_3
–
23
D2_3
+
24
216210f
3
LTC2162/LTC2161/LTC2160
converTer characTerisTics
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Transition Noise
Internal Reference
External Reference
External Reference
Differential Analog Input
(Note 6)
Differential Analog Input
(Note 7)
Internal Reference
External Reference
CONDITIONS
l
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C.
LTC2162
MIN
16
–6
–0.9
–7
–1.8
±2
±0.5
±1.5
±1.5
–0.5
±10
±30
±10
3.3
6
0.9
7
0.8
TYP
MAX
MIN
16
–6
–0.9
–7
–1.8
±2
±0.5
±1.5
±1.5
–0.5
±10
±30
±10
3.3
6
0.9
7
0.8
LTC2161
TYP
MAX
MIN
16
–6
–0.9
–7
–1.8
±2
±0.5
±1.5
±1.5
–0.5
±10
±30
±10
3.2
6
0.9
7
0.8
LTC2160
TYP
MAX
UNITS
Bits
LSB
LSB
mV
%FS
%FS
µV/°C
ppm/°C
ppm/°C
LSB
RMS
analog inpuT
SYMBOL
V
IN
V
IN(CM)
V
SENSE
I
INCM
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
PARAMETER
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
External Reference Mode
Per Pin, 65Msps
Per Pin, 40Msps
Per Pin, 25Msps
0 < A
IN+
, A
IN–
< V
DD
0 < PAR/SER < V
DD
0.625 < SENSE < 1.3V
Single-Ended Encode
Differential Encode
Figure 6 Test Circuit
l
l
l
l
l
l
MIN
0.7
0.625
TYP
1 to 2
V
CM
1.250
104
64
40
MAX
1.25
1.300
UNITS
V
P-P
V
V
µA
µA
µA
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
External Voltage Reference Applied to SENSE
Analog Input Common Mode Current
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
–1
–3
–3
0
0.07
0.09
80
550
1
3
3
µA
µA
µA
ns
ps
RMS
dB
MHz
DynaMic accuracy
SYMBOL PARAMETER
SNR
Signal-to-Noise Ratio
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
LTC2162
CONDITIONS
5MHz Input
30MHz Input
70MHz Input
140MHz Input
l
LTC2161
MAX
MIN
75.3
TYP
76.9
76.8
76.7
76.2
90
90
89
84
MAX
MIN
75.5
LTC2160
TYP
77.1
77.0
76.9
76.4
90
90
89
84
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
216210f
MIN
75.4
TYP
77.0
76.9
76.8
76.3
90
90
89
84
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd Harmonic
30MHz Input
70MHz Input
140MHz Input
l
82
83
83
4
LTC2162/LTC2161/LTC2160
DynaMic accuracy
SYMBOL PARAMETER
SFDR
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
LTC2162
CONDITIONS
l
LTC2161
MAX
MIN
84
TYP
90
90
89
84
95
95
95
95
76.7
76.6
76.3
75.2
MAX
MIN
84
LTC2160
TYP
90
90
89
84
95
95
95
95
76.9
76.8
76.5
76.4
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
MIN
83
TYP
90
90
89
84
95
95
95
95
76.8
76.7
76.4
76.3
Spurious Free Dynamic Range 5MHz Input
3rd Harmonic
30MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
30MHz Input
70MHz Input
140MHz Input
5MHz Input
30MHz Input
70MHz Input
140MHz Input
SFDR
l
88
89
89
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
l
75
75
74.9
inTernal reFerence characTerisTics
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400µA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–600µA < I
OUT
< 1mA
I
OUT
= 0
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
MIN
0.5•V
DD
– 25mV
TYP
0.5•V
DD
±25
4
1.225
1.250
±25
7
0.6
1.275
MAX
0.5•V
DD
+ 25mV
UNITS
V
ppm/°C
Ω
V
ppm/°C
Ω
mV/V
DigiTal inpuTs anD ouTpuTs
SYMBOL
PARAMETER
ENCODE INPUTS (ENC
+
, ENC
–
)
DIFFERENTIAL ENCODE MODE (ENC
–
NOT TIED TO GND)
V
ID
V
ICM
V
IN
R
IN
C
IN
V
IH
V
IL
V
IN
R
IN
C
IN
Differential Input Voltage
Common Mode Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
编译自semiengineering 业界越来越关注人工智能的功耗问题，但这个问题并没有简单的解决方案。这需要深入了解应用、半导体和系统层面的软件和硬件架构，以及所有这些的设计和实现方式。每个环节都会影响总功耗和提供的效用。这是最终必须做出的权衡。 但首先，必须解决效用问题。电力是否被浪费了？“我们将电力用于有价值的用途，”Ansys（现为新思科技旗下公司）产品营销总监 Marc Swi...[详细]
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