NCP51400, NCV51400
3 Amp V
TT
Termination
Regulator DDR1, DDR2,
DDR3, LPDDR3, DDR4
The NCP51400 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration.
The NCP51400 maintains a fast transient response and only requires
a minimum output capacitance of 20
mF.
The NCP51400 supports
a remote sensing function and all power requirements for DDR V
TT
bus termination. The NCP51400 can also be used in low−power
chipsets and graphics processor cores that require dynamically
adjustable output voltages.
The NCP51400 is available in the thermally−efficient DFN10
Exposed Pad package, and is rated both Green and Pb−free.
Features
www.onsemi.com
DFN10, 3x3, 0.5P
CASE 506CL
MARKING DIAGRAM
51400
ALYWG
G
51400 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
For Automotive Applications
Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails
PV
CC
Voltage Range: 1.1 V to 3.5 V
Integrated Power MOSFETs
Fast Load−Transient Response
P
GOOD
− Logic output pin to Monitor V
TT
Regulation
EN − Logic input pin for Shutdown mode
V
RI
− Reference Input Allows for Flexible Input Tracking Either
Directly or Through Resistor Divider
Remote Sensing (V
TTS
)
Built−in Soft Start, Under Voltage Lockout and Over Current Limit
Thermal Shutdown
Small, Low−Profile 10−pin, 3x3 DFN Package
NCV51400MWTXG − Wettable Flank Option for Enhanced Optical
Inspection
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
These Devices are Pb−Free and are RoHS Compliant
PIN CONNECTION
V
RI
PV
CC
V
TT
P
GND
V
TTS
1
2
3
4
5
GND
+
10
9
8
7
6
V
CC
P
GOOD
GND
EN
V
RO
Exposed Pad
Applications
DDR Memory Termination
Desktop PC’s, Notebooks, and Workstations
Servers and Networking equipment
Telecom/Datacom, GSM Base Station
Graphics Processor Core Supplies
Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
Chipset/RAM Supplies as Low as 0.5 V
Active Bus Termination
ORDERING INFORMATION
Device
NCP51400MNTXG
NCV51400MNTXG*
NCV51400MWTXG*
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
DFN10
(Pb−Free)
3000 / Tape &
Reel
Package
Shipping
†
©
Semiconductor Components Industries, LLC, 2016
1
June, 2016 − Rev. 4
Publication Order Number:
NCP51400/D
NCP51400, NCV51400
PIN FUNCTION DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
Pin Name
V
RI
PV
CC
V
TT
P
GND
V
TTS
V
RO
EN
GND
P
GOOD
V
CC
THERMAL
PAD
Pin Function
V
TT
External Reference Input ( set to V
DDQ
/ 2 thru resistor network ).
Power input. Internally connected to the output source MOSFET.
Power Output of the Linear Regulator.
Power Ground. Internally connected to the output sink MOSFET.
V
TT
Sense Input. The V
TTS
pin provides accurate remote feedback sensing of V
TT
. Connect V
TTS
to the
remote DDR termination bypass capacitors.
Independent Buffered V
TT
Reference Output. Sources and sinks over 5 mA. Connect to GND thru
0.1
mF
ceramic capacitor.
Shutdown Control Input. CMOS compatible input. Logic high = enable, logic low = shutdown. Connect
to V
DDQ
for normal operation.
Common Ground.
Power Good (Open Drain output).
Analog power supply input. Connect to GND thru a 1 − 4.7
mF
ceramic capacitor.
Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple
vias for maximum power dissipation performance.
ABSOLUTE MAXIMUM RATINGS
Rating
V
CC
, PV
CC
, V
TT
, V
TTS
, V
RI
, V
RO
(Note 1)
EN, P
GOOD
(Note 1)
P
GND
to GND (Note 1)
Storage Temperature
Operating Junction Temperature Range
ESD Capability, Human Body Model (Note 2)
T
STG
T
J
ESD
HBM
Symbol
Value
−0.3 to 6.0
−0.3 to 6.0
−0.3 to +0.3
−55 to 150
150
2000
Unit
V
V
V
°C
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following method:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
DISSIPATION RATINGS
Package
10−Pin DFN
T
A
= 255C Power Rating
1.92 W
Derating Factor above
T
A
= 255C
19 mW/°C
T
A
= +855C Power Rating
0.79 W
THERMAL INFORMATION
NCP51400 (*)
DFN 3x3mm
10 pins
53.9
95.5
32.3
4.3
32.3
14.2
Symbol
R
qJA
R
qJC(top)
R
qJB
Y
JT
Y
JB
R
qJC(bot)
Thermal Metric
Junction−to−ambient thermal resistance
Junction−to−case (top) thermal resistance
Junction−to−board thermal resistance (1mm from package)
Junction−to−top thermal resistance
Junction−to−board thermal resistance (1mm from package)
Junction−to−case (bot) thermal resistance
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
*1S2P JEDEC JESD51−7 PCB with 240 sqmm, 2 oz copper heat spreader.
www.onsemi.com
2
NCP51400, NCV51400
RECOMMENED OPERATING CONDITIONS
Rating
Supply Voltage
Voltage Range
Symbol
V
CC
V
RO
V
RI
PV
CC
, V
TT
, V
TTS
, EN, P
GOOD
P
GND
Operating Free−Air Temperature
T
A
Value
2.375 to 5.5
−0.1 to 1.8
0.5 to 1.8
−0.1 to 3.5
−0.1 to +0.1
−40 to +125
°C
Unit
V
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
−40°C
≤
T
A
≤
125°C; V
CC
= 3.3 V; PV
CC
= 1.8 V; V
RI
= V
TTS
= 0.9 V; EN = V
CC
; C
OUT
= 3 x 10
mF
(Ceramic); unless otherwise noted.
Parameter
Supply Current
V
CC
Supply Current
V
CC
Shutdown Current
T
A
= +25°C, EN = 3.3 V, No Load
T
A
= +25°C, EN = 0 V, V
RI
= 0 V, No Load
T
A
= +25°C, EN = 0 V, V
RI
> 0.4 V, No Load
V
CC
UVLO Threshold
Wake−up, T
A
= +25°C
Hysteresis
PV
CC
Supply Current
PV
CC
Shutdown Current
V
TT
Output
V
TT
Output DC Voltage
PV
CC
= 1.50 V, V
RO
= 0.75 V, I
TT
= 0 A
PV
CC
= 1.35 V, V
RO
= 0.675 V, I
TT
= 0 A
PV
CC
= 1.20 V, V
RO
= 0.60 V, I
TT
= 0 A
V
TT
Output Voltage Tolerance to
V
RO
PV
CC
= 1.50 V, V
RO
= 0.75 V,
−2 A < I
TT
< 2 A
PV
CC
= 1.35 V, V
RO
= 0.675 V,
−2 A < I
TT
< 2 A
PV
CC
= 1.20 V, V
RO
= 0.60 V, −2 A < I
TT
<
2A
Source Current Limit
Sink Current Limit
Soft−start Current Limit Timeout
Discharge MOSFET On−resist-
ance
V
RI
− Input Reference
V
RI
Voltage Range
V
RI
Input−bias Current
V
RI
UVLO Voltage
EN = 3.3 V
V
RI
rising
Hysteresis
V
RO
− Output Reference
V
RO
Voltage
V
RI
V
V
RI
I
RI
V
RI UVLO
V
RI HYS
360
390
60
0.5
1.8
+1
435
V
mA
mV
V
RI
= 0 V, V
TT
= 0.3 V, EN = 0 V, T
A
= +25°C
V
TTS
= 90% * V
RO
V
TTS
= 110% * V
RO
T
SS
R
DIS
3
3.5
200
18
25
V
OS
0.75
0.675
0.60
±18
±20
±20
4.5
5.5
A
A
ms
W
mV
V
T
A
= +25°C, EN = 3.3 V, No Load
T
A
= +25°C, EN = 0 V, No Load
I
PVCC
I
PVCC SHD
V
UVLO
2.15
I
VCC
I
VCC SHD
0.7
65
200
2.3
50
1
0.1
50
50
1
80
400
2.375
V
mV
mA
mA
mA
mA
Conditions
Symbol
Min
Typ
Max
Unit
www.onsemi.com
3
NCP51400, NCV51400
ELECTRICAL CHARACTERISTICS
−40°C
≤
T
A
≤
125°C; V
CC
= 3.3 V; PV
CC
= 1.8 V; V
RI
= V
TTS
= 0.9 V; EN = V
CC
; C
OUT
= 3 x 10
mF
(Ceramic); unless otherwise noted.
Parameter
V
RO
Voltage Tolerance to V
RI
Conditions
−10 mA < I
RO
< 10 mA, V
RI
= 1.25 V
−10 mA < I
RO
< 10 mA, V
RI
= 0.9 V
−10 mA < I
RO
< 10 mA, V
RI
= 0.75 V
−10 mA < I
RO
< 10 mA, V
RI
= 0.6 V
V
RO
Source Current Limit
V
RO
Sink Current Limit
P
GOOD
− Powergood Comparator
P
GOOD
Lower Threshold
P
GOOD
Upper Threshold
P
GOOD
Hysteresis
P
GOOD
Start−up Delay
P
GOOD
Leakage Current
P
GOOD
= False Delay
P
GOOD
Output Low Voltage
EN − Enable Logic
Logic Input Threshold
EN Logic high
EN Logic low
Hysteresis Voltage
Logic Leakage Current
Thermal Shutdown
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
T
SD
T
SH
150
25
°C
°C
EN pin
EN pin, T
A
= +25°C
V
IH
V
IL
V
ENHYS
I
ILEAK
−1
0.5
+1
1.7
0.3
V
mA
V
Start−up rising edge, V
TTS
within 15% of
V
RO
V
TTS
= V
RI
(P
GOOD
= True)
P
GOOD
= V
CC
+ 0.2 V
V
TTS
is beyond
±20%
P
GOOD
trip thresholds
I
GOOD
= 4 mA
10
0.4
(with respect to V
RO
)
(with respect to V
RO
)
−23.5
%
17.5%
−20%
20%
5%
2
1
ms
mA
ms
V
−17.5
%
23.5%
V/V
V
RO
= 0 V
V
RO
= 0 V
Symbol
Min
−15
−15
−15
−15
10
10
40
40
Typ
Max
+15
+15
+15
+15
mA
mA
Unit
mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
4
NCP51400, NCV51400
Figure 1. Typical DDR−3 Application Schematic
Figure 2. Block Diagram
www.onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
