MTP3N60E
Designer’s™ Data Sheet
TMOS E−FET.™
High Energy Power FET
N−Channel Enhancement−Mode Silicon
Gate
This advanced high voltage TMOS E−FET is designed to withstand
high energy in the avalanche mode and switch efficiently. This new
high energy device also offers a drain−to−source diode with fast
recovery time. Designed for high voltage, high speed switching
applications such as power supplies, PWM motor controls and other
inductive loads, the avalanche energy capability is specified to
eliminate the guesswork in designs where inductive loads are switched
and offer additional safety margin against unexpected voltage
transients.
•
Avalanche Energy Capability Specified at Elevated
Temperature
•
Low Stored Gate Charge for Efficient Switching
•
Internal Source−to−Drain Diode Designed to Replace External Zener
Transient Suppressor — Absorbs High Energy in the Avalanche
Mode
•
Source−to−Drain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode
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TMOS POWER FET
3.0 AMPERES, 600 VOLTS
R
DS(on)
= 2.2
W
TO-220AB
CASE 221A−09
Style 5
D
®
G
S
Preferred
devices are Motorola recommended choices for future use and best overall value.
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 3
1
Publication Order Number:
MTP3N60E/D
MTP3N60E
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−Source Voltage
Drain−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−Source Voltage — Continuous
Gate−Source Voltage
— Non−repetitive
Drain Current — Continuous
Drain Current
— Continuous @ 100°C
Drain Current
— Pulsed
Total Power Dissipation @ T
C
= 25°C
Derate above 25°C
Operating and Storage Temperature Range
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
Value
600
600
±
20
±
40
3.0
2.4
14
75
0.6
−55
to 150
Unit
Vdc
Vdc
Vdc
Vpk
Adc
I
DM
P
D
T
J
, T
stg
Watts
W/°C
°C
UNCLAMPED DRAIN−TO−SOURCE AVALANCHE CHARACTERISTICS
(T
J
< 150°C)
Single Pulse Drain−to−Source Avalanche Energy — T
J
= 25°C
Single Pulse Drain−to−Source Avalanche Energy
— T
J
= 100°C
Repetitive Pulse Drain−to−Source Avalanche Energy
W
DSR(1)
W
DSR(2)
290
46
7.5
mJ
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case°
Thermal Resistance
— Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) V
DD
= 50 V, I
D
= 3.0 A
(2) Pulse Width and frequency is limited by T
J
(max) and thermal response
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
R
θJC
R
θJA
T
L
1.67
62.5
260
°C/W
°C
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MTP3N60E
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0, I
D
= 250
μAdc)
Zero Gate Voltage Drain Current
(V
DS
= 600 V, V
GS
= 0)
(V
DS
= 480 V, V
GS
= 0, T
J
= 125°C)
Gate−Body Leakage Current — Forward (V
GSF
= 20 Vdc, V
DS
= 0)
Gate−Body Leakage Current — Reverse (V
GSR
= 20 Vdc, V
DS
= 0)
ON CHARACTERISTICS*
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
μAdc)
(T
J
= 125°C)
Static Drain−to−Source On−Resistance (V
GS
= 10 Vdc, I
D
= 1.5 A)
Drain−to−Source On−Voltage (V
GS
= 10 Vdc)
(I
D
= 3.0 A)
(I
D
= 1.5 A, T
J
= 100°C)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 1.5 A)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS*
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
Forward On−Voltage
Forward Turn−On Time
Reverse Recovery Time
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
* Pulse Test: Pulse Width = 300
μs,
Duty Cycle
≤
2.0%.
** Limited by circuit inductance.
L
d
nH
—
—
—
3.5
4.5
7.5
—
—
—
(I
S
= 3.0 A, di/dt = 100 A/μs)
(V
DS
= 420 V, I
D
= 3.0 A,
V
GS
= 10 V)
(V
DD
= 300 V, I
D
≈
3.0 A,
R
L
= 100
Ω,
R
G
= 12
Ω,
V
GS(on)
= 10 V)
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
V
SD
t
on
t
rr
—
—
—
—
—
—
—
—
—
—
23
34
58
35
28
5.0
17
—
**
400
—
—
—
—
31
—
—
1.4
—
—
Vdc
ns
nC
ns
(V
DS
= 25 V, V
GS
= 0,
f = 1.0 MHz)
C
iss
C
oss
C
rss
—
—
—
770
105
19
—
—
—
pF
V
GS(th)
Vdc
2.0
1.5
—
—
—
1.5
—
—
2.1
—
—
—
4.0
3.5
2.2
9.0
7.5
—
mhos
Ohms
Vdc
V
(BR)DSS
I
DSS
600
—
—
Vdc
μAdc
Symbol
Min
Typ
Max
Unit
—
—
—
—
—
—
—
—
10
100
100
100
I
GSSF
I
GSSR
nAdc
nAdc
R
DS(on)
V
DS(on)
g
FS
SOURCE−DRAIN DIODE CHARACTERISTICS
L
s
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MTP3N60E
TYPICAL ELECTRICAL CHARACTERISTICS
VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED
8
1.2
V
DS
= V
GS
I
D
= 0.25 mA
V
GS
= 10 V
7V
I D, DRAIN CURRENT (AMPS)
1.1
6
1
4
6V
2
5V
0
0
2
8
12
16
6
10
14
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
4
18
20
0.9
0.8
0.7
−50
−25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
1
Figure 1. On−Region Characteristics
VBR(DSS), DRAIN−TO−SOURCE BREAKDOWN VOLTAGE
(NORMALIZED)
Figure 2. Gate−Threshold Voltage Variation
With Temperature
10
1.2
V
GS
= 0
I
D
= 250
μA
I D, DRAIN CURRENT (AMPS)
8
V
DS
≥
10 V
1.1
6
1
4
100°C
2
T
J
= 25°C
0.9
0.8
−55°C
8
9
0
0
1
2
4
6
3
5
7
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
−50
−25
0
25
50
75
100
125
1
T
J
, JUNCTION TEMPERATURE (°C)
Figure 3. Transfer Characteristics
Figure 4. Breakdown Voltage Variation
With Temperature
RDS(on) , DRAIN−TO−SOURCE ON−RESISTANCE
(NORMALIZED)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
6
V
GS
= 10 V
100°C
3
V
GS
= 10 V
I
D
= 2 A
2
4
T
J
= 25°C
2
−55°C
1
0
0
2
4
6
8
10
I
D
, DRAIN CURRENT (AMPS)
0
−50
−25
0
25
50
75
100
125
1
T
J
, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance versus Drain Current
Figure 6. On−Resistance Variation
With Temperature
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MTP3N60E
SAFE OPERATING AREA INFORMATION
100
I D, DRAIN CURRENT (AMPS)
I D, DRAIN CURRENT (AMPS)
V
GS
= 20 V
SINGLE PULSE
T
C
= 25°C
10
100
μs
10 ms
dc
1
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
1
100
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
1 ms
16
10
μs
12
8
T
J
≤
150°C
4
0
0
600
200
400
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
80
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
Figure 8. Maximum Rated Switching
Safe Operating Area
The power averaged over a complete switching cycle
must be less than:
T
J(max)
−
T
C
R
θJC
10000
V
DD
= 300 V
I
D
= 3 A
V
GS(on)
= 10 V
T
J
= 25°C
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain−to−source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of
linear systems. The curves are based on a case
temperature of 25°C and a maximum junction temperature
of 150°C. Limitations for repetitive pulses at various case
temperatures can be determined by using the thermal
response curves. Motorola Application Note, AN569,
“Transient Thermal Resistance−General Data and Its Use”
provides detailed instructions.
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 8 is
the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamental limits
are the peak current, I
DM
and the breakdown voltage,
V
(BR)DSS
. The switching SOA shown in Figure 8 is
applicable for both turn−on and turn−off of the devices for
switching times less than one microsecond.
t
d(off)
1000
t, TIME (ns)
t
f
100
t
r
10
1
10
100
R
G
, GATE RESISTANCE (OHMS)
t
d(on)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
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