NBA3N206S
3.3 V Automotive Grade
M-LVDS Driver Receiver
Description
The NBA3N206S is a 3.3 V supply differential Multipoint Low
Voltage (M−LVDS) line Driver and Receiver for automotive
applications. NBA3N206S offers the Type 2 receiver threshold at
0.1 V.
The NBA3N206S has Type−2 receivers that detect the bus state with
as little as 50 mV of differential input voltage over a common−mode
voltage range of −1 V to 3.4 V. Type−2 receivers include an offset
threshold to provide a detectable voltage under open−circuit, idle−bus,
and other faults conditions.
NBA3N206S supports Simplex or Half Duplex bus configurations.
Features
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MARKING
DIAGRAM
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
NA206
A
Y
WW
G or
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
NA206
AYWW
G
•
Low−Voltage Differential 30
W
to 55
W
Line Drivers and Receivers
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
for Signaling Rates Up to 200 Mbps
Type−2 Receivers Provide an Offset (100 mV) Threshold to Detect
Open−Circuit and Idle−Bus Conditions
Controlled Driver Output Voltage Transition Times for Improved
Signal Quality
−1 V to 3.4 V Common−Mode Voltage Range Allows Data Transfer
With up to 2 V of Ground Noise
Bus Pins High Impedance When Disabled or VCC
≤
1.5 V
M−LVDS Bus Power Up/Down Glitch Free
Operating range: VCC = 3.3
±10%
V( 3.0 to 3.6 V)
Operation from –40°C to +125°C.
AEC−Q100 Qualified and PPAP Capable
These are Pb−Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Applications
Low−Power High−Speed Short−Reach Alternative to TIA/EIA−485
Backplane or Cabled Multipoint Data and Clock Transmission
Cellular Base Stations
Central−Office Switches
Network Switches and Routers
Automotive
©
Semiconductor Components Industries, LLC, 2015
1
October, 2015 − Rev. 3
Publication Order Number:
NBA3N206S/D
NBA3N206S
R
RE
1
8 V
CC
7 B
2
DE
3
6 A
D
4
SOIC−8
5 GND
Figure 1. Logic Diagram
Figure 2. Pinout Diagram
(Top View)
Table 1. PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
Name
R
RE
DE
D
GND
A
B
VCC
M−LVDS Input
/Output
M−LVDS Input
/Output
I/O Type
LVCMOS Output
LVCMOS Input
LVCMOS Input
LVCMOS Input
High
Low
Open Default
Receiver Output Pin
Receiver Enable Input Pin (LOW = Active, HIGH = High Z
Output)
Driver Enable Input Pin (LOW = High Z Output, HIGH=Active)
Driver Input Pin
Ground Supply pin. Pin must be connected to power supply to
guarantee proper operation.
Transceiver True Input /Output Pin
Transceiver Invert Input /Output Pin
Power Supply pin. Pin must be connected to power supply to
guarantee proper operation.
Description
Table 2. DEVICE FUNCTION TABLE
Inputs
V
ID
= V
A
− V
B
V
ID
w
150 mV
TYPE 2 Receiver
50 mV < V
ID
< 150 mV
V
ID
≤
50 mV
X
X
Open
Input
D
L
DRIVER
H
Open
X
X
RE
L
L
L
H
Open
L
Enable
DE
H
H
H
Open
L
A/Y
L
H
L
Z
Z
Output
R
H
?
L
Z
Z
L
Output
B/Z
H
L
H
Z
Z
H = High, L = Low, Z = High Impedance, X = Don’t Care, ? = Indeterminate
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NBA3N206S
Table 3. ATTRIBUTES
(Note 1)
Characteristics
Human Body Model (JEDEC
Standard 22, Method A114−A)
ESD
Protection
Machine Model
Charged –Device Model (JEDEC
Standard 22, Method C101)
A, B
All Pins
All Pins
All Pins
Value
±6
kV
±2
kV
±200
V
±1500
V
Level 1
UL−94 code V−0 A 1/8”
28 to 34
917 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
IN
Supply Voltage
Input Voltage
D, DE, RE
A, B
I
OUT
Parameter
Condition 1
Condition 2
Rating
−0.5
≤
V
CC
≤
4.0
−0.5
≤
V
IN
≤
4.0
−1.8
≤
V
IN
≤
4.0
−0.3
≤
I
OUT
≤
4.0
−1.8
≤
I
OUT
≤
4.0
−40 to
≤
+125
−65 to +150
Unit
V
V
Output Voltage
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Power Dissipation (Continuous)
R
A, B
V
°C
°C
°C/W
°C/W
°C/W
°C
mW
mW/°C
mW
T
A
T
stg
θ
JA
θ
JC
T
sol
P
D
0 lfpm
500 lfpm
(Note 2)
SOIC−8
SOIC−8
190
130
41 to 44
265
T
A
= 25°C
25°C < T
A
< 125°C
T
A
= 125°C
725
5.8
377
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NBA3N206S
Table 5. DC CHARACTERISTICS
VCC = 3.3
±10%
V( 3.0 to 3.6 V), GND = 0 V, T
A
= −40°C to +125°C (See Notes 4, 5)
Symbol
ICC
Characteristic
Power Supply Current
Receiver Disabled Driver Enabled RE and DE at V
CC
, R
L
= 50
W,
All others open
Driver and Receiver Disabled RE at VCC, DE at 0 V, R
L
= No Load, All others open
Driver and Receiver Enabled RE at 0 V, DE at V
CC
, R
L
= 50
W,
All others open
Receiver Enabled Driver Disabled RE at 0 V, DE at 0 V, R
L
= 50
W,
All others open
Input HIGH Voltage
Input LOW Voltage
Voltage at any bus terminal VA, VB, VY or VZ
Magnitude of differential input voltage
Differential output voltage magnitude (see Figure 4)
Change in Differential output voltage magnitude between logic states (see Figure 4)
Steady state common mode output voltage (see Figure 5)
Change in Steady state common mode output voltage between logic states (see
Figure 5)
Peak−to−peak common−mode output voltage (see Figure 5)
Maximum steady−state open−circuit output voltage (see Figure 9)
Maximum steady−state open−circuit output voltage (see Figure 9)
Voltage overshoot, low−to−high level output (see Figure 7)
Voltage overshoot, high−to−low level output (see Figure 7)
High−level input current (D, DE) V
IH
= 2 V
Low−level input current (D, DE) V
IL
= 0.8 V
Differential short−circuit output current magnitude (see Figure 6)
High−impedance state output current (driver only)
−1.4 V
≤
(VA or VB)
≤
3.8 V, other output at 1.2 V
Power−off output current (0 V
≤
V
CC
≤
1.5 V)
−1.4 V
≤
(VA or VB)
≤
3.8 V, other output at 1.2 V
Positive−going Differential Input voltage Threshold (See Figure 11 & Table 8)
Type 2
V
IT−
V
HYS
VOH
VOL
I
IH
I
IL
I
OZ
C
A
/ C
B
C
AB
C
A/B
Negative−going Differential Input voltage Threshold (See Figure 11 & Table 8)
Type 2
Differential Input Voltage Hysteresis (See Figure 11 and Table 2)
Type 2
High−level output voltage (IOH = –8 mA
Low−level output voltage (IOL = 8 mA)
RE
High-level
input current (VIH = 2 V)
RE
Low-level
input current (VIL = 0.8 V)
High−impedance state output current (VO = 0 V of 3.6 V)
Input Capacitance VI = 0.4
impedance analyzer (or equivalent)
sin(30E
6
πt)
+ 0.5 V, other outputs at 1.2 V using HP4194A
−10
−10
−10
3
2.5
99
101
2.4
0.4
0
0
15
0
V
V
mA
mA
mA
pF
pF
%
50
mV
150
mV
−15
−10
−0.2 V
SS
0
0
10
10
24
10
10
0
0
2
GND
−1.4
0.05
440
−50
0.8
−50
Min
Typ
13
1
16
Max
22
4
24
13
V
CC
0.8
3.8
V
CC
690
50
1.2
50
150
2.4
2.4
1.2 V
SS
mV
mV
V
mV
mV
V
V
V
V
uA
uA
mA
uA
uA
V
V
V
Unit
mA
V
IH
V
IL
VBUS
|VID|
DRIVER
|V
AB
|
D|V
AB
|
V
OS(SS)
DV
OS(SS)
V
OS(PP)
V
AOC
V
BOC
V
P(H)
V
P(L)
I
IH
I
IL
JI
OS
J
I
OZ
I
O(OFF)
RECEIVER
V
IT+
mV
Differential Input Capacitance V
AB
= 0.4 sin(30E
6
πt)
V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
Input Capacitance Balance, (C
A
/C
B
)
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NBA3N206S
Table 5. DC CHARACTERISTICS
VCC = 3.3
±10%
V( 3.0 to 3.6 V), GND = 0 V, T
A
= −40°C to +125°C (See Notes 4, 5)
Typ
(Note
4)
Symbol
BUS INPUT AND OUTPUT
I
A
Characteristic
Min
Max
Unit
Input Current Receiver or Transceiver with Driver Disabled
V
A
= 3.8 V, V
B
= 1.2 V
V
A
= 0.0 V or 2.4 V, V
B
= 1.2 V
V
A
= −1.4 V, V
B
= 1.2 V
0
−20
−32
0
−20
−32
−4
0
−20
−32
0
−20
−32
−4
5
5
3.0
32
20
0
uA
I
B
Input Current Receiver or Transceiver with Driver Disabled
V
B
= 3.8 V, V
A
= 1.2 V
V
B
= 0.0 V or 2.4 V, V
A
= 1.2 V
V
B
= −1.4 V, V
A
= 1.2 V
32
20
0
uA
I
AB
I
A(OFF)
Differential Input Current Receiver or Transceiver with driver disabled (I
A
−I
B
)
V
A
= V
B
, −1.4
≤
V
A
≤
3.8 V
Input Current Receiver or Transceiver Power Off 0V
≤
V
CC
≤
1.5 and:
V
A
= 3.8 V, V
B
= 1.2 V
V
A
= 0.0 V or 2.4 V, V
B
= 1.2 V
V
A
= −1.4 V, V
B
= 1.2 V
Input Current Receiver or Transceiver Power Off 0V
≤
V
CC
≤
1.5 and:
V
B
= 3.8 V, V
A
= 1.2 V
V
B
= 0.0 V or 2.4 V, V
A
= 1.2 V
V
B
= −1.4 V, V
A
= 1.2 V
Receiver Input or Transceiver Input/Output Power Off Differential Input Current; (I
A
−I
B
)
V
A
= V
B
, 0
≤
V
CC
≤
1.5 V, −1.4
≤
V
A
≤
3.8 V
Transceiver Input Capacitance with Driver Disabled V
A
= 0.4 sin(30E
6
πt)
+ 0.5 V using
HP4194A impedance analyzer (or equivalent); V
B
= 1.2 V
Transceiver Input Capacitance with Driver Disabled V
B
= 0.4 sin(30E
6
πt)
+ 0.5 V using
HP4194A impedance analyzer (or equivalent); V
A
= 1.2 V
Transceiver Differential Input Capacitance with Driver Disabled V
A
= 0.4 sin(30E
6
pt)
+
0.5 V using HP4194A impedance analyzer (or equivalent);
V
B
= 1.2 V
Transceiver Input Capacitance Balance with Driver Disabled, (C
A
/C
B
)
uA
4
uA
32
20
0
uA
32
20
0
uA
4
pF
pF
pF
I
B(OFF)
I
AB(OFF)
C
A
C
B
C
AB
C
A/B
99
101
%
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. See Figure 3. DC Measurements reference.
4. Typ value at 25°C and 3.3 VCC supply voltage.
Table 6. DRIVER AC CHARACTERISTICS
VCC = 3.3
±10%
V( 3.0 to 3.6 V), GND = 0 V, T
A
= −40°C to +125°C (Note 5)
Symbol
t
PLH
/ t
PHL
t
PHZ
/ t
PLZ
t
PZH
/ t
PZL
t
SK(P)
t
SK(PP)
t
JIT(PER)
t
JIT(PP)
Characteristic
Propagation Delay (See Figure 7)
Disable Time HIGH or LOW state to High Impedance (See Figure 8)
Enable Time High Impedance to HIGH or LOW state (See Figure 8)
Pulse Skew (|t
PLH
− t
PHL
|) (See Figure 7)
Device to Device Skew similar path and conditions (See Figure 7)
Period Jitter RMS, 100 MHz (Source tr/tf 0.5 ns, 10 and 90 % points, 30k sam-
ples. Source jitter de−embedded from Output values ) (See Figure 10)
Peak−to−peak Jitter, 200 Mbps 2
15
−1 PRBS (Source tr/tf 0.5 ns, 10 and 90%
points, 100k samples. Source jitter de−embedded from Output values) (See
Figure 10)
Differential Output rise and fall times (See Figure 7)
0.9
2
30
0
Min
1.0
Typ
1.5
Max
2.4
7
7
150
1
3.5
150
Unit
ns
ns
ns
ps
ns
ps
ps
tr / tf
1.6
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
5. Typ value at 25°C and 3.3 V
CC
supply voltage.
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