SN54/74LS174
HEX D FLIP-FLOP
The LSTTL / MSI SN54 / 74LS174 is a high speed Hex D Flip-Flop. The
device is used primarily as a 6-bit edge-triggered storage register. The
information on the D inputs is transferred to storage during the LOW to HIGH
clock transition. The device has a Master Reset to simultaneously clear all
flip-flops. The LS174 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all Motorola TTL families.
HEX D FLIP-FLOP
LOW POWER SCHOTTKY
•
•
•
•
Edge-Triggered D-Type Inputs
Buffered-Positive Edge-Triggered Clock
Asynchronous Common Reset
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
Q5
15
D5
14
D4
13
Q4
12
D3
11
Q3
10
CP
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
16
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
1
1
MR
2
Q0
3
D0
4
D1
5
Q1
6
D2
7
Q2
8
GND
PIN NAMES
LOADING
(Note a)
16
HIGH
D0 – D5
CP
MR
Q0 – Q5
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
LOGIC SYMBOL
LOGIC DIAGRAM
3 4 6 11 13 14
MR CP D5
1
9
14
D4
13
D3
11
D2
6
D1
4
D0
3
9
1
D Q
CP
CD
15
D Q
CP
CD
12
D Q
CP
CD
10
D Q
CP
CD
7
D Q
CP
CD
5
D Q
CP
CD
D0 D1 D2 D3 D4 D5
CP
MR
Q0 Q1 Q2 Q3 Q4 Q5
2 5 7 10 12 15
2
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
Q5
Q4
Q3
Q2
Q1
Q0
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-1
SN54/74LS174
FUNCTIONAL DESCRIPTION
The LS174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and Master
Reset (MR) are common to all flip-flops.
Each D input’s state is transferred to the corresponding flip-
flop’s output following the LOW to HIGH Clock (CP) transition.
A LOW input to the Master Reset (MR) will force all outputs
LOW independent of Clock or Data inputs. The LS174 is
useful for applications where the true output only is required
and the Clock and Master Reset are common to all storage
elements.
TRUTH TABLE
Inputs (t = n, MR = H)
D
H
L
Note 1: t = n + 1 indicates conditions after next clock.
Outputs (t = n+1) Note 1
Q
H
L
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
– 20
– 0.4
– 100
26
0.35
0.5
20
IIH
IIL
IOS
ICC
V
µA
mA
mA
mA
mA
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-2
SN54/74LS174
AC CHARACTERISTICS
(TA = 25°C)
Limits
Symbol
fMAX
tPHL
tPLH
tPHL
Parameter
Maximum Input Clock Frequency
Propagation Delay, MR to Output
Propagation Delay, Clock to Output
Min
30
Typ
40
23
20
21
35
30
30
Max
Unit
MHz
ns
ns
VCC = 5.0 V
CL = 15 pF
Test Conditions
AC SETUP REQUIREMENTS
(TA = 25°C)
Limits
Symbol
tW
ts
th
trec
Parameter
Clock or MR Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Min
20
20
5.0
25
Typ
Max
Unit
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
AC WAVEFORMS
1/fmax
tw
CP
1.3 V
ts(H)
D
*
1.3 V
t
th(H)s(L)
1.3 V
tPLH
1.3 V
1.3 V
th(L)
1.3 V
tPHL
1.3 V
MR
1.3 V
tW
1.3 V
trec
1.3 V
CP
Q
tPHL
1.3 V
1.3 V
Q
*The shaded areas indicate when the input is permitted to
*change
for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
FAST AND LS TTL DATA
5-3
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