FM24V05
512Kb Serial 3V F-RAM Memory
Features
512K bit Ferroelectric Nonvolatile RAM
Organized as 65,536 x 8 bits
High Endurance 100 Trillion (10
14
) Read/Writes
10 year Data Retention
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
Up to 3.4 MHz maximum bus frequency
Direct hardware replacement for EEPROM
Supports legacy timing for 100 kHz & 400 kHz
Device ID
Device ID reads out Manufacturer ID & Part ID
Low Voltage, Low Power Operation
Low Voltage Operation 2.0V – 3.6V
Active Current < 150 A (typ.
@ 100KHz
)
90 A Standby Current (typ.)
5 A Sleep Mode Current (typ.)
Industry Standard Configuration
Industrial Temperature -40 C to +85 C
8-pin “Green”/RoHS SOIC Package
Description
The FM24V05 is a 512Kbit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
The FM24V05 performs write operations at bus
speed. No write delays are incurred. The next bus
cycle may commence immediately without the need
for data polling. In addition, the product offers write
endurance orders of magnitude higher than
EEPROM. Also, F-RAM exhibits much lower power
during writes than EEPROM since write operations
do not require an internally elevated power supply
voltage for write circuits.
These capabilities make the FM24V05 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.
The FM24V05 provides substantial benefits to users
of serial EEPROM, yet these benefits are available in
a hardware drop-in replacement. The devices are
available in industry standard 8-pin SOIC package
using a familiar two-wire (I
2
C) protocol. Both
devices incorporate a read-only Device ID that allows
the host to determine the manufacturer, product
density, and product revision. The devices are
guaranteed over an industrial temperature range of -
40°C to +85°C.
Pin Configuration
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
Pin Name
A0-A2
SDA
SCL
WP
VDD
VSS
Function
Device Select Address
Serial Data/address
Serial Clock
Write Protect
Supply Voltage
Ground
This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s
internal qualification testing and has reached production status.
Cypress Semiconductor Corporation
•
Document Number: 001-84462 Rev. *B
198 Champion Court
•
San Jose, CA 95134-1709 • 408-943-2600
Revised May 29, 2013
FM24V05 - 512Kb I2C FRAM
Counter
Address
Latch
8K x 64
FRAM Array
8
SDA
Serial to Parallel
Converter
Data Latch
8
Control Logic
Device ID and
Serial Number
SCL
WP
A0-A2
Figure 1. FM24V05 Block Diagram
Pin Description
Pin Name
A0-A2
Type
Input
Pin Description
Device Select Address 0-2: These pins are used to select one of up to 8 devices of
the same type on the same two-wire bus. To select the device, the address value on
the two pins must match the corresponding bits contained in the slave address. The
address pins are pulled down internally.
Serial Data/Address: This is a bi-directional pin for the two-wire interface. It is
open-drain and is intended to be wire-OR‟d with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. An external pull-up resistor is
required.
Serial Clock: The serial clock pin for the two-wire interface. Data is clocked out of
the part on the falling edge, and into the device on the rising edge. The SCL input
also incorporates a Schmitt trigger input for noise immunity.
Write Protect: When tied to VDD, addresses in the entire memory map will be write-
protected. When WP is connected to ground, all addresses may be written. This pin
is pulled down internally.
Supply Voltage
Ground
SDA
I/O
SCL
Input
WP
Input
VDD
VSS
Supply
Supply
Document Number: 001-84462 Rev. *B
Page 2 of 17
FM24V05 - 512Kb I2C FRAM
Overview
The FM24V05 is a family of serial F-RAM memory
devices. The memory array is logically organized as a
65,536 x 8 bit memory array and is accessed using an
industry standard two-wire (I
2
C) interface. Functional
operation of the F-RAM is similar to serial
EEPROM. The major difference between the
FM24V05 and serial EEPROM is F-RAM‟s superior
write performance.
Two-wire Interface
The FM24V05 employs a bi-directional two-wire bus
protocol using few pins or board space. Figure 2
illustrates a typical system configuration using the
FM24V05 in a microcontroller-based system. The
industry standard two-wire bus is familiar to many
users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24V05 always is a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including start, stop, data bit, or acknowledge. Figure
3 illustrates the signal conditions that specify the four
states. Detailed timing diagrams are shown in the
electrical specifications section.
VDD
Memory Architecture
When accessing the FM24V05, the user addresses
65,536 locations each with 8 data bits. These data bits
are shifted serially. The 65,536 addresses are
accessed using the two-wire protocol, which includes
a slave address (to distinguish other non-memory
devices) and a 2-byte address. All 16 address bits are
used by the decoder for accessing the memory.
The access time for memory operation is essentially
zero beyond the time needed for the serial protocol.
That is, the memory is read or written at the speed of
the two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. That is, by the time a
new bus transaction can be shifted into the part, a
write operation will be complete. This is explained in
more detail in the interface section below.
Users expect several obvious system benefits from
the FM24V05 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note that it is the user‟s responsibility to ensure that
V
DD
is within datasheet tolerances to prevent
incorrect operation.
Microcontroller
R
min
= 1.1 K
ohm
R
max
= t
R/Cbus
SDA
SCL
SDA
SCL
FM24V05
A0
A1
A2
FM24V05
A0
A1
A2
Figure 2. Typical System Configuration
Document Number: 001-84462 Rev. *B
Page 3 of 17
FM24V05 - 512Kb I2C FRAM
SCL
SDA
Stop
(Master)
Start
(Master)
7
6
0
Data bit Acknowledge
(Transmitter) (Receiver)
Data bits
(Transmitter)
Figure 3. Data Transfer Protocol
Stop Condition
A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24V05 should end
with a stop condition. If an operation is in progress
when a stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a stop condition.
Start Condition
A start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All commands should be preceded by a start
condition. An operation in progress can be aborted by
asserting a start condition at any time. Aborting an
operation using the start condition will ready the
FM24V05 for a new operation.
If during operation the power supply drops below the
specified V
DD
minimum, the system should issue a
start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The acknowledge takes place after the 8
th
data bit has
been transferred in any transaction. During this state
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
no-acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the no-acknowledge ceases the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24V05 will
continue to place data onto the bus as long as the
receiver sends acknowledges (and clocks). When a
read operation is complete and no more data is
needed, the receiver must not acknowledge the last
byte. If the receiver acknowledges the last byte, this
will cause the FM24V05 to attempt to drive the bus
on the next clock while the master is sending a new
command such as stop.
Slave Address
The first byte that the FM24V05 expects after a start
condition is the slave address. As shown in Figure 4,
the slave address contains the device type or slave
ID, the device select address bits, a page address bit,
and a bit that specifies if the transaction is a read or a
write.
Bits 7-4 are the device type (slave ID) and should be
set to 1010b for the FM24V05. These bits allow other
function types to reside on the 2-wire bus within an
identical address range. Bits 3-1 are the device select
address bits. They must match the corresponding
value on the external address pins to select the
device. Up to eight FM24V05 devices can reside on
the same two-wire bus by assigning a different
address to each. Bit 0 is the read/write bit. R/W=1
indicates a read operation and R/W=0 indicates a
write operation.
High Speed Mode (HS-mode)
The FM24V05 supports a 3.4MHz high speed mode.
A master code (0000 1
XXX
b) must be issued to place
the device into high speed mode. Communication
between master and slave will then be enabled for
speeds up to 3.4MHz. A stop condition will exit HS-
mode. Single- and multiple-byte reads and writes are
supported. See Figures 10 and 11 for HS-mode
timings.
Document Number: 001-84462 Rev. *B
Page 4 of 17
FM24V05 - 512Kb I2C FRAM
Memory Operation
Slave ID
Device Select
1
7
0
6
1
5
0
4
A2
3
A1
2
A0
1
R/W
0
Figure 4. Slave Address
Addressing Overview
After the FM24V05 (as receiver) acknowledges the
slave address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The complete 16-bit address is
latched internally. Each access causes the latched
address value to be incremented automatically. The
current address is the value that is held in the latch --
either a newly written value or the address following
the last access. The current address will be held for as
long as power remains or until a new value is written.
Reads always use the current address. A random read
address can be loaded by beginning a write operation
as explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24V05 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (FFFFh) is reached, the address latch will
roll over to 0000h. There is no limit to the number of
bytes that can be accessed with a single read or write
operation.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24V05 can begin. For a read operation the
FM24V05 will place 8 data bits on the bus then wait
for an acknowledge from the master. If the
acknowledge occurs, the FM24V05 will transfer the
next sequential byte. If the acknowledge is not sent,
the FM24V05 will end the read operation. For a write
operation, the FM24V05 will accept 8 data bits from
the master then send an acknowledge. All data
transfer occurs MSB (most significant bit) first.
The FM24V05 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of F-RAM
technology. These improvements result in some
differences between the FM24V05 and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Write Operation
All writes begin with a slave address, then a memory
address. The bus master indicates a write operation
by setting the LSB of the slave address (R/W bit) to a
„0‟. After addressing, the bus master sends each byte
of data to the memory and the memory generates an
acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
from FFFFh to 0000h.
Unlike other nonvolatile memory technologies, there
is no effective write delay with F-RAM. Since the
read and write access times of the underlying
memory are the same, the user experiences no delay
through the bus. The entire memory cycle occurs in
less time than a single bus clock. Therefore, any
operation including read or write can occur
immediately following a write. Acknowledge polling,
a technique used with EEPROMs to determine if a
write is complete is unnecessary and will always
return a ready condition.
Internally, an actual memory write occurs after the 8
th
data bit is transferred. It will be complete before the
acknowledge is sent. Therefore, if the user desires to
abort a write without altering the memory contents,
this should be done using start or stop condition prior
to the 8
th
data bit. The FM24V05 uses no page
buffering.
The memory array can be write-protected using the
WP pin. This feature is available only on FM24V05
devices. Setting the WP pin to a high condition (V
DD
)
will write-protect all addresses. The FM24V05 will
not acknowledge data bytes that are written to
protected addresses. In addition, the address counter
will not increment if writes are attempted to these
addresses. Setting WP to a low state (V
SS
) will
deactivate this feature. WP is pulled down internally.
Figures 5 and 6 below illustrate a single-byte and
multiple-byte write cycles.
Document Number: 001-84462 Rev. *B
Page 5 of 17
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