Si9978DW
Vishay Siliconix
Si9978
Configurable H-Bridge Driver
FEATURES
• H-Bridge or Dual Half-Bridge Operation • Cross-Conduction Protected
• 20- to 40-V Supply
• Current Limit
• Static (dc) Operation
• Undervoltage Lockout
• ESD Protected
• Fault Output
DESCRIPTION
The Si9978DW is an integrated driver for an n-channel
MOSFET H-bridge. The mode control allows operation as
either a full H-bridge driver or as two independent
half-bridges. The DIR/PWM input configuration allows easy
implementation of either sign/magnitude or anti-phase PWM
drive schemes for full H-bridges. Schmitt triggers on the
inputs provide logic signal compatibility and hysteresis for
increased noise immunity. An internal low-voltage regulator
allows the device to be powered directly from a system supply
of 20 to 40 volts. All n-channel gates are driven directly from
low-impedance outputs. The addition of one external
capacitor per half-bridge allows internal circuitry to level shift
both the power supply and logic signal for the high-side
n-channel gate drives. Internal charge pumps replace leakage
current lost in the high-side driver circuits to provide “static”
(dc) operation in any output condition. Protection features
include an undervoltage lockout, cross-conduction prevention
logic, and overcurrent monitors.
The Si9978DW is available in the 24-pin wide-body SOIC
(surface mount) package, specified to operate over the
industrial (-40 to +85°C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
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S-60752—Rev. D, 05-Apr-99
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Si9978DW
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltage on pins 2-7 with respect to ground. . . . . . -0.3 to V
DD
+ 0.3 V
Voltage on pin 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 50 V
Voltage on pins 17, 19, 21, 23 . . . . . . . . . . . . . . . . . . . . -0.3 to +60 V
Voltage on pins 18, 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2 to 50 V
Operating Temperature (T
A
) . . . . . . . . . . . . . . . . . . . . . . . -40 to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Maximum Junction Temperature (T
J
) . . . . . . . . . . . . . . . . . . . . . 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
RECOMMENDED OPERATING CONDITIONS
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 to 40 V
DC
R
A
, R
B
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 kΩ
SPECIFICATIONS
Limits
Test Conditions
Unless Otherwise Specified
Parameter
Power
Supply Voltage Range
Logic Voltage
Supply Current
V+
V
DD
I+
I
DD
= 0 mA
20
14.5
16
3
40
17.5
5
V
mA
-40 to 85°C
Symbol
V+ = 20 to 40 V
Min
a
Typ
b
Max
a
Unit
Inputs (DIR, PWM, EN, QS, MODE, BRK)
High-State
Low-State
High-State Input Current
Low-State Input Current
V
IH
V
IL
I
IH
I
IL
V
IH
= V
DD
V
IL
= 0 V
-100
-50
4.0
1.0
10
-25
V
µA
Outputs
Low-Side Gate Drive, High State
Low-Side Gate Drive, Low State
High-Side Gate Drive, High State
High-Side Gate Drive, Low State
Capacitor
Voltage
c
V
GBH
V
GBL
V
GTH
V
GTL
V
CAP
t
rL
t
fL
t
rH
t
fH
V
OL
I
OH
I
OL
= 1 mA
FAULT, CL = V
DD
0.2
Rise Time = 1 to 10 V
Fall Time = 10 to 1 V
C
L
= 600 pF
S
A, B
= 0 V
V+ = 40 V
14
16
14
16
17.5
1
18
1
55
110
50
110
50
250
0.4
10
V
µA
ns
V
Low-Side Switching, Rise Time
Low-Side Switching, Fall Time
High-Side Switching, Rise Time
High-Side Switching, Fall Time
Break-Before-Make Time
FAULT, CL
FAULT, CL Leakage Current
Protection
Low-Side Undervoltage Lockout
Low-Side Hysteresis
High-Side Undervoltage Lockout
UVLL
V
H
UVLH
S
A, B
= 0 V
0.8 V
DD
0.8
V
DD
-3.3 V
V
S-60752—Rev. D, 05-Apr-99
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Si9978DW
Vishay Siliconix
SPECIFICATIONS
Limits
Test Conditions
Unless Otherwise Specified
Parameter
Current Limit
Comparator Input Bias Current
Comparator Threshold Voltage
I
IB
V
TH
t
p
t
pd
T
A
= 25°C
R
A
, R
B
= 100 kΩ, C
A
, C
B
= 100 pF
R
A
, R
B
= 100 kΩ, C
A
, C
B
= 0.001 µF
C
L
= 600 pF
-5
90
85
8
80
10
100
600
-0.2
100
5
110
115
12
120
µA
mV
-40 to 85°C
Symbol
V+ = 20 to 40 V
Min
a
Typ
b
Max
a
Unit
One Shot Pulse Width
Propagation Delay
Notes:
µs
ns
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. V
CAP
= (V+) + (V
DD
)
TRUTH TABLE
H-BRIDGE MODEL
MODE
1
1
1
1
1
1
1
1
DIR/
IN
A
1
1
0
0
X
X
X
X
EN/
EN
A
1
1
1
1
1
0
1
X
QS/
IN
B
1
0
1
0
X
X
X
X
X
X
X
X
PWM/
EN
B
BRK
0
0
0
0
1
X
0
X
X
IL
A
+
L
L
L
L
L
L
IL
B
+
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
L
L
L
K
L
L
L
GT
A
H
GB
A
L
L
GT
B
L
L
H
L
L
H
L
L
L
1
0
GB
B
CL/
FAULT
B
1
1
1
1
1
1
FAULT/
FAULT
A
1
1
1
1
1
1
Brake
Disable
Overcurrent
Undervoltage
on V
DD
Normal
Operation
Condition
HALF-BRIDGE MODEL
MODE
0
0
0
0
0
0
0
DIR/
IN
A
1
0
X
X
X
X
X
EN/
EN
A
1
1
0
0
1
X
X
QS/
IN
B
X
X
1
0
X
X
X
PWM/
EN
B
0
0
1
1
X
1
X
BRK
X
X
X
X
X
X
X
X
X
X
IL
A
+
L
L
L
L
IL
B
+
L
L
L
L
X
GT
A
H
L
L
L
L
X
L
GB
A
L
H
L
L
L
X
L
GT
B
L
L
H
L
X
L
L
GB
B
L
L
L
H
X
L
L
0
CL/
FAULT
B
1
1
1
1
1
1
0
FAULT/
FAULT
A
1
1
1
1
Overcurrent on
A
Overcurrent on
B
Undervoltage
on V
DD
Normal
Operation
Condition
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S-60752—Rev. D, 05-Apr-99
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Si9978DW
Vishay Siliconix
PIN CONFIGURATION
PIN DESCRIPTION
Pin 1: V
DD
V
DD
is an internally generated voltage. It is connected to this
pin to allow connection of a decoupling capacitor. A minimum
of 1 µF is recommended.
Pin 2: EN/EN
A
The EN input allows normal operation when at logic “1”, and
turns all gate drive outputs off when at logic “0”. When the
mode pin is at logic “1”, EN controls the entire H-bridge. When
the mode pin is at logic “0”, this pin becomes the ENABLE pin
for half-bridge A.
Pin 3: DIR/IN
A
The function of this pin is determined by the MODE pin.
When the MODE pin is at logic “1”, it is the DIR pin, and when
MODE is at logic “0”, it is the IN
A
pin.
As the DIR input, it is the direction control for the H-bridge,
and determines which diagonal pair of power MOSFETs is
active. A logic “1” turns on GT
A
and enables GB
B
, while a logic
“0” turns on GT
B
and enables GB
A
. When implementing an
anti-phase PWM control, the DIR input serves as the PWM
input.
As the IN
A
pin, it is the input that controls the “A” half-bridge.
When at logic “1”, the high-side MOSFET is turned on, and
when at logic “0”, the low-side MOSFET is turned on.
Pin 4: PWM/EN
B
With the mode pin at logic “1”, this pin is the PWM input. It
controls the switching of the active diagonal pair. A logic “1”
S-60752—Rev. D, 05-Apr-99
4
turns the active MOSFETs on, while a logic “0” turns it off. The
QS input determines whether the bottom or both bottom and
top MOSFETs are switched. When implementing an
anti-phase PWM control, the PWM input is connected to a
logic “1”. When the mode pin is at logic “0”, this pin becomes
the ENABLE pin for half-bridge B.
Pin 5: QS/IN
B
With the mode pin at logic “1”, this input determines whether
the bottom MOSFETs of the H-bridge or both bottom and top
MOSFETs switch in response to the PWM signal. A logic “1”
on this input enables only the bottom MOSFETs. This is the
default condition as this pin is pulled up internally. When this
pin is pulled to ground, both the bottom and top MOSFETs are
enabled.
This input controls the B half-bridge when the MODE pin is at
logic “0”. When at logic “1”, the high-side MOSFET is turned
on, and when at logic “0”, the low-side MOSFET is turned on.
Pin 6: MODE
This input determines whether the Si9978 functions as an
H-bridge or as two independent half-bridges. When the
MODE pin is at logic “1”, the Si9978 functions as an H-bridge,
and when MODE is at logic “0”, it functions as two
independent half-bridges.
Pin 7: BRK
When this input and MODE are at logic “1”, both bottom gate
drives are switched high, turning on the bottom MOSFETs.
When this input is at logic “0”, the Si9978 operates normally.
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Pin 8: CL/FAULT
B
This is an open drain output which is active low. When the
MODE pin is at logic “1”, this pin functions as CL and
indicates that the H-bridge is in current limit. It stays low for
the duration of the current limit one-shot. With the MODE pin
at logic “0”, it serves as the FAULT output for half-bridge B to
indicate when an undervoltage or overcurrent condition is
detected. When indicating an overcurrent condition, the output
stays low for the duration of the current limit one-shot. The
FAULT output resets automatically when the condition clears.
Pin 9: FAULT/FAULT
A
This is an open drain output which is switched low when an
undervoltage or overcurrent condition is detected. When
indicating an overcurrent condition, the output stays low for
the duration of the current limit one-shot. When the MODE
pin is at logic “1”, this pin is the H-bridge FAULT output. With
the MODE pin at logic “0”, it serves as the FAULT output for
half-bridge A. The FAULT output resets automatically when
the condition clears.
Pin 10: NC
No internal connection.
Pin 11: R
A
/C
A
The timing resistor and capacitor for the current limit one-shot
are connected to this pin. The values of the resistor and
capacitor determine the off time set by the one-shot. The
one-shot is triggered when the current limit comparator
detects an overcurrent condition.
Pin 12: R
B
/C
B
The timing resistor and capacitor for the current limit one-shot
are connected to this pin. The values of the resistor and
capacitor determine the off time set by the one-shot. The
one-shot is triggered when the current limit comparator
detects an overcurrent condition.
Pin 13: IL
A
+ and Pin 14, IL
B
+
These are the overcurrent sense inputs. Internally, they are
connected to the noninverting inputs of the current limit
comparators. Externally they are connected to the source(s)
of the low-side MOSFET(s) and the current sense resistor.
Pin 15: GND
The GND pin is the ground return for V+ and the ground
reference for the logic. Also, this is the ground reference input
for the current limit comparators and is connected to the
ground side of the internal 100-mV references. This pin
should be connected directly to the ground side of the current
sensing resistors.
Pin 16: GB
B
and Pin 20, GB
A
These pins drive the gates of the low-side power MOSFETs.
Pin 17: GT
B
and Pin 21, GT
A
These pins drive the gates of the high-side power MOSFETs.
Pin 18: S
B
and Pin 22, S
A
These are the source connections of the high-side power
MOSFETs, the drain of the external low-side power MOSFET,
the negative terminal of the bootstrap capacitor, and the
output for each half-bridge.
Pin 19: CAP
B
and Pin 23, CAP
A
These are the connections for the positive terminals of the
bootstrap capacitors C
BA
and C
BB
. A 0.01-µF capacitor can
be used for most applications.
Pin 24: V+
This is the only external power supply required for the
Si9978DW, and must be the same supply used to power the
H-bridge it is driving. The Si9978DW powers the low-voltage
logic, low-side gate driver, and bootstrap/ charge pump
circuits from self-contained voltage regulators which require
only a bootstrap capacitor on the CAP pins.
No voltage sensing circuitry monitors V+ directly; however, the
low-voltage, internally generated supply and the bootstrap
voltage (which are derived from V+) are directly protected by
undervoltage monitors.
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S-60752—Rev. D, 05-Apr-99
5
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