a. Device mounted with all leads soldered or welded to PC board.
b. Derate 7.2 mW/_C above 25_C.
* . Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause permanent
damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any
one time
SPECIFICATIONS
Test Conditions Unless Specified
Parameter
Supply
Quiescent Current
I
Q
ENABLE =Logic Low
4
8
mA
Limits
0 to 70_C
Symbol
2.9 V
v
V
DD
v
13.2 V
HI/LO = GND R
BIAS
= 12.5 kW
GND,
12 5
L
BOOST
= 100
mH,
C
BOOST
= 100 nF
Min
a
Typ
b
Max
a
Unit
Logic
Enable Turn-On Voltage
Enable Turn-Off Voltage
Enable Source Current
Turn-On Time
Turn-Off Time
Turn-On Boost
t
OFF
Initial Short Circuit
t
OFF
Short Circuit
Status Output Voltage
Status Output Delay Time
Status Threshold
HI/LO Turn-On Voltage
HI/LO Turn-Off Voltage
V
EN(on)
V
EN(off)
I
ENSRC
t
ON
t
OFF
t
ON(BST)
t
OFF(ISC)
t
OFF(SC)
V
STAT
t
STDLY
V
STATTHR
V
HILO(on)
V
HILO(off)
V
ENABLE
= 0V
See Figure 3
See Figure 4
C
GATE
= 33 nF, See Figure 6
C
GATE
= 33 nF, See Figure 7
I
SINK
= 200
mA
See Figure 8
0.85 x V
DD
0.7 x V
DD
0.3 x V
DD
0.7 x V
DD
40
120
5
5
600
10
2
0.4
25
0.95 x V
DD
V
V
ms
m
ms
0.3 x V
DD
V
mA
Gate Drive
Enhancement Voltage (V
GATE
−
V
SENSE
)
Source Current
Sink Current
V
GS
I
SOURCE
I
SINK
V
CBOOST
= 9 V
8.5
1.06
1.6
10.5
1.30
2.6
15
1.54
3.7
V
mA
Current Sense Circuit
Current Sense Amplifier Common Mode
Range
Current Sense Amplifier Voltage Offset
Current Sense Amplifier Bias Current
R
LIMSET
Reference Current
Current Sense Amplifier Hysteresis
Current Sense Amplifier Series Offset
V
CMR
V
OS
I
SOS
I
RLIMSET
V
HYST
V
SOS
HI/LO = V
DD
, V
CMR
> 0.5 V
Normal Operation
18
0
−3
−0.2
19.5
12
20
21
V
DD
+ 0.3
3
V
mV
mA
mV
Power On Reset
RESET Output Voltage
RESET Output Hysteresis
c
RESET Comparator Input Threshold
www.vishay.com
V
OP(rst)
V
HYST
V
RST
I
OUT
= 1 mA, V
DD
> 2 V
See Note c
2
1.223
1.250
1.277
0.4
V
mV
V
2
Document Number: 70028
S-40754—Rev. D, 19-Apr-04
Si9750
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
Parameter
Power On Reset
RESET Comparator Offset Voltage
d
RESET Comparator Input Bias Current
RESET Timer Delay
RETRY
V
RBIAS
I
BIAS
t
RSTD
t
RETRY
C
RST
= 15 nF, See Figure 8
C
RETRY
= 100 nF
110
70
0.5
−0.2
150
130
190
200
mV
mA
ms
ms
Limits
0 to 70_C
Symbol
2.9 V
v
V
DD
v
13.2 V
HI/LO = GND, R
BIAS
= 12.5 kW
L
BOOST
= 100
mH,
C
BOOST
= 100 nF
Min
a
Typ
b
Max
a
Unit
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production test.
c. In a practical situation, V
HYST
is multiplied by ratio of a resistor divider chain. For V
DD
= 13.2 V, V
HYST
= 20 mV.
d. The RESET comparator input threshold specification (V
RST
) includes theRESET comparator offset voltage.
PIN CONFIGURATION AND ORDERING INFORMATION
SOIC-16
BOOST
V
DD
GATE
LOAD
SENSE
LIMSET
HI/LO
ENABLE
1
2
3
4
5
6
7
8
Top View
16
15
14
13
12
11
10
9
COIL
GND
C
RST
C
RETRY
RESET
STATUS
V
RST
R
BIAS
ORDERING INFORMATION
Part Number
Si9750CY
Si9750CY-T1
Si9750CY-T1—E3
0 to 70_C
SOIC-16
Temperature Range
Package
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
BOOST
V
DD
GATE
LOAD
SENSE
LIMSET
HI/LO
ENABLE
R
BIAS
V
RST
STATUS
RESET
C
RETRY
C
RST
GND
COIL
Positive supply pin.
Connection to external power MOSFET gate.
Connection to positive supply side of LOAD.
Description
Output of on-chip Boost converter. A 100-nF capacitor should be connected between BOOST and GND
Connects external sense resistor of a sensefet sense pin to SENSE input of overcurrent trip comparator. A standard
MOSFET may also be used in conjunction with a low ohmic value shunt resistor.
Connects overcurrent limit set resistor R
LIMSET
to the reference input of overcurrent trip comparator.
CMOS logic input to control the overcurrent trip comparator sensitivity at power-on. HI/LO should be connected to GND
for low Capacitive loads and to V
DD
for high capacitive loads.
CMOS logic input to turn IC on or off. GATE voltage remains low when ENABLE is high.
A resistor connected from this pin to GND programs the reference bias current for the overcurrent trip comparator
resistor R
LIMSET
and the GATE
(on)
charge current. See Functional Description for equations.
Input to voltage monitor comparator.
Open drain NMOS output. This pin is driven low when the current limiter is enabled and the LOAD voltage is greater than
90% of V
DD
.
Open drain NMOS output. This pin is driven low during power on reset or when V
RST
is lower than the internal 1.25-V
reference.
A capacitor connected from this pin to GND programs the retry timer.
A capacitor connected from this pin to GND programs the reset timer.
Negative supply pin.
Connection to Boost converter inductor.
www.vishay.com
Document Number: 70028
S-40754—Rev. D, 19-Apr-04
3
Si9750
Vishay Siliconix
FUNCTIONAL DESCRIPTION
The Si9750 together with an n-channel MOSFET provides the
following functions:
D
limits di/dt current for hot insertion applications
D
provides complete short circuit protection
D
high-side drive allows n-channel MOSFET to be
used, for lower power dissipation
D
industry-standard microprocessor reset function
D
logic control input and outputs
I
LOAD
x R
SENSE
>1.2 x I
BIAS
x R
LIMSET
+ I
BIAS
(1 kW + R
HI
)
(HI/LO = High)
(3)
I
LOAD
x R
SENSE
> 1.2 x I
BIAS
x R
LIMSET
(with pin HI/LO=Low)
(2)
If the HI/LO pin is tied low the current limit is 20% higher during
turn-on than the steady state current limit point.
If a higher current limit is needed at start-up, the HI/LO pin can
be tied high. The equation becomes:
Setting the Current Limit
(SENSE, HI/LO pins, R
LIMSET
, R
SENSE
)
The current limit point is determined by the voltage across
R
SENSE
, the value of R
LIMSET
, and the bias current. The
current limit circuit is shown in Figure 1
The steady state current is set by the equation:
Notice that any current limit can be set at turn-on using an
optional resistor, R
HI
.
Relaxation Mode Current Limit
(C
RETRY
pin)
In an overload condition, the Si9750 will go into a relaxation
mode current limit operation that not only protects the source
and load, but also reduces the power dissipated in the
MOSFET. When an overload is detected, the circuit quickly
turns off, then goes into a retry mode whereby the current is
ramped up slowly. If the fault still exists, the current will ramp
down again. This sequence will repeat indefinitely at a period
defined by 10
6
x C
RETRY
until the fault is removed. Typically,
capacitors in the range of 1 nF to 1
mF
can be used on C
RETRY
,
but the period should be >50 ms.
I
LOAD
x R
SENSE
> I
BIAS
x R
LIMSET
(1)
Due to the highly capacitive nature of some loads, the Si9750
has an option to increase the current limit point to a much
higher level at turn-on. In this case, turn-on is defined as V
GATE
< V
DD
+ 7.8 V. This function is implemented with the HI/LO pin.
Si9750
Overcurrent
I
BIAS
HI/LO
−
+
1 kW,
"20%
SENSE
GATE
R
HI
(Optional)
R
SENSE
V
DD
330
W
33 nF
330
W
LIMSET
R
LIMSET
HI/LO
I
LOAD
V
LOAD
FIGURE 1.
www.vishay.com
4
Document Number: 70028
S-40754—Rev. D, 19-Apr-04
Si9750
Vishay Siliconix
FUNCTIONAL DESCRIPTION (CONT’D)
di/dt Limiting On Hot and Cold Insertion (GATE pin)
The GATE pin provides a constant current source that is used
to control the rate of rise of the gate of the MOSFET, and hence
to control the di/dt of the load and source current. The equation
that governs the gate current is:
I
SOURCE
+
1.25 V x
(for R
BIAS
= 12.5 kW)
12
+
1.2 mA
R
BIAS
boost inductor should typically be 100
mH,
<3.5
W,
>180 mA
dc, and the boost capacitor should be 100 nF.
Logic Control
(STATUS, ENABLE, RESET, V
RST
and C
RST
pins)
STATUS.
The status monitor detects when the load voltage is
90% of input voltage, V
LOAD
> 0.9 x V
DD
. This pin is an
open-drain NMOS output, capable of sinking 200
mA
at V
OL
=
0.4 V. If this pin is used in conjunction with the ENABLE of
another unit, power supply sequencing (or daisy-chaining) is
easily implemented.
ENABLE.
This CMOS logic compatible input serves as the
on/off control pin. This pin has 40-mA minimum pull-up to V
DD
.
(4)
Typically, a 33-nF capacitor should be connected from the
GATE pin to ground. If a large I
SOURCE
is needed for high di/dt,
a 330-W resistor in series with C
GATE
may be necessary to
prevent oscillation. In the case that V
DD
> 6 V, a resistor of
approximately 330
W
is also recommended in series with the
gate. (Figure 1)
Reference Bias Current
(R
BIAS
pin)
This pin sets the internal current used by R
LIMSET
to determine
all the current limit points. Typically R
BIAS
= 12.5 kW which sets
a 20-mA bias current. The equation which relates R
BIAS
to I
BIAS
is:
RESET (V
RST
, C
RST
, RESET pins).
This is a standard
implementation of the microprocessor reset function. A
comparator looks at the voltage on V
RST
pin and compares it
with 1.25 V. This function is programmable by using an
external voltage divider. When V
RST
is higher than 1.25 V, the
reset signal is delayed by the C
RST
pin, defined by Equation (6)
and then goes high. (Figure 2)
I
BIAS
+
1.25 V
+
20
mA
5 x R
BIAS
Reset delay t
RSTD
[
10
4
x C
RST
(5)
(6)
(for R
BIAS
= 12.5 kW)
Power on Reset (POR)
(V
DD
pin)
This function monitors the voltage on the V
DD
pin and signals
the system if all input voltage requirements have been met. At
turn-on when V
DD
> 2.7 V
"
200 mV, a POR signal is
generated for a duration of 100
ms.
After this point the system
is released into operation. If V
DD
falls below 2.7 V
"
200 mV,
a second POR signal will be generated. If two POR signals are
detected, this indicates that the source for V
DD
is not capable
of supplying the load current. The IC then turns off the
MOSFET and initiates its retry period, hence fully protecting
the MOSFET from an over-power condition.
Current
HI/LO Pin
R
LIMSET
C
RETRY
Short Circuit
Applied to Output
Turn-On
V
GATE
> V
DD
+ 7.8 V
Current Limit Point
I
LOAD
Boost Converter
(COIL, BOOST pins)
The boost converter generates the gate drive for the external
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