a. Device mounted with all leads soldered or welded to PC board.
b. Derate 8.3 mW/_C above T
A
= 25_C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typical values for dropout voltage at V
OUT
w
2 V are measured at
V
OUT
= 3.3 V, while typical values for dropout voltage at V
OUT
< 2 V are measured at V
OUT
= 1.8 V.
d. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-V
differential, provided that V
IN
does not not drop below 2.0 V.
e. The device’s shutdown pin includes a typical 6-MW internal pull-down resistor connected to ground.
f.
V
OUT
is defined as the output voltage of the DUT at 1 mA.
g. The Error Output (Low) function is guaranteed from V
OUT
= 2.0 V to V
OUT
= 5.0 V.
h. The Power_Good trip threshold function is guaranteed from V
OUT
= 1.5 V to V
OUT
= 5.0 V and V
IN
w
2.0 V.
Document Number: 71119
S-50955—Rev. F, 16-May-05
www.vishay.com
3
Si9181
Vishay Siliconix
TIMING WAVEFORMS
V
IN
t
ON
V
NOM
0.95 V
NOM
V
OUT
ERROR
t
DELAY
FIGURE 4.
Timing Diagram for Power-Up
PIN CONFIGURATION
TSSOP-8
C
NOISE
DELAY
GND
V
IN
1
2
3
4
Top View
8
7
6
5
SD
ERROR
SENSE or ADJ
V
OUT
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
www.vishay.com
Name
C
NOISE
DELAY
GND
V
IN
V
OUT
SENSE or ADJ
ERROR
SD
Function
Noise bypass pin. For low noise applications, a 0.01-mF or larger ceramic capacitor should be connected from this pin
to ground.
Capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the ERROR (Pin 7) output.
Refer to Figure 4.
Ground pin. Local ground for C
NOISE
and C
OUT
.
Input supply pin. Bypass this pin with a 2.2-mF ceramic or tantalum capacitor to ground.
Output voltage. Connect C
OUT
between this pin and ground.
For fixed output voltage versions, this pin should be connected to V
OUT
(Pin 5). For adjustable output voltage version,
this voltage feedback pin sets the output voltage via an external resistor divider.
This open drain output is an error flag output which goes low when V
OUT
drops 5% below its nominal voltage. This pin
also provides a power-on-reset signal if a capacitor is connected to the DELAY pin.
By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to V
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