Si6924EDQ
Vishay Siliconix
N-Channel 2.5-V (G-S) Battery Switch, ESD Protection
PRODUCT SUMMARY
V
DS
(V)
28
r
DS(on)
(W)
0.033 @ V
GS
= 4.5 V
0.038 @ V
GS
= 3.0 V
0.042 @ V
GS
= 2.5 V
I
D
(A)
"4.6
"4.3
"4.1
ESD Protected
2000 V
FEATURES
D
D
D
D
Low r
DS(on)
V
GS
Max Rating: 14 V
Exceeds 2-kV ESD Protection
Low Profile TSSOP-8 Package
D
r
DS(on)
Rating at 2.5-V V
GS
D
28-V V
DS
Rated
D
Symetrical Voltage Blocking (Off Voltage)
DESCRIPTION
The Si6924EDQ is a dual n-channel MOSFET with ESD
protection and gate over-voltage protection circuitry
incorporated into the MOSFET. The device is designed for use
in Lithium Ion battery pack circuits. The common-drain
contsruction takes advantage of the typical battery pack
topology, allowing a further reduction of the device’s
on-resistance. The 2-stage input protection circuit is a unique
design, consisting of two stages of back-to-back zener diodes
separated by a resistor. The first stage diode is designed to
absorb most of the ESD energy. The second stage diode is
designed to protect the gate from any remaining ESD energy
and over-voltages above the gates inherent safe operating
range. The series resistor used to limit the current through the
second stage diode during over voltage conditions has a
maximum value which limits the input current to
v
10 mA @
14 V and the maximum t
off
to 12
ms.
The Si6924EDQ has been
optimized as a battery or load switch in Lithium Ion applications
with the advantage of both a 2.5-V r
DS(on)
rating and a safe
14-V gate-to-source maximum rating.
APPLICATION CIRCUITS
D
ESD and
Overvoltage
Protection
ESD and
Overvoltage
Protection
R**
G
S
**R typical value is 1.8 kW by design.
Battery Protection Circuit
See Typical Characteristics,
Gate-Current vs. Gate-Source Voltage, Page 3.
*Thermal connection to drain pins is required to achieve specific performance.
FIGURE 1.
Typical Use In a Lithium Ion Battery Pack
Document Number: 70814
S-59522—Rev. C, 30-Nov-98
FIGURE 2.
Input ESD and Overvoltage Protection
Circuit.
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1
Si6924EDQ
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
*D
*D
TSSOP-8
D
S
1
S
1
G
1
1
2
3
4
Top View
S
1
N-Channel
N-Channel
S
2
D
8 D
7 S
2
6 S
2
5 G
2
1.8 kW
G
1
G
2
1.8 kW
Si6924EDQ
*Thermal connection to drain pins is required to achieve specific performance.
FIGURE 3.
FIGURE 4.
ABSOLUTE MAXIMUM RATINGS (T
A
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Drain-Source Voltage, Source-Drain Voltage
Gate-Source Voltage
Continuous Drain-to-Source Current (T
J
= 150_C)
a, b
_
Pulsed Drain-to-Source Current
Pulsed Source Current (Diode Conduction)
a, b
Maximum Power Dissipation
a, b
Operating Junction and Storage Temperature Range
T
A
= 25_C
T
A
= 70_C
T
A
= 25_C
T
A
= 70_C
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
stg
Limit
- to +
"14
"4.6
"3.7
"20
1.25
1.1
0.72
-55 to 150
Unit
V
A
W
_C
THERMAL RESISTANCE RATINGS
Parameter
t
v
10 sec
Maximum
Junction-to-Ambient
a
Steady-State
R
thJA
115
Symbol
Typical
Maximum
125
Unit
_C/W
Notes
a. Surface Mounted on FR4 Board.
b. t
v
10 sec.
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Document Number: 70814
S-59522—Rev. C, 30-Nov-98
2
Si6924EDQ
Vishay Siliconix
SPECIFICATIONS (T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= 250
mA
V
DS
= 0 V, V
GS
=
"4.5
V
Gate-Body Leakage
I
GSS
V
DS
= 0 V, V
GS
=
"14
V
V
DS
= 22.4 V, V
GS
= 0 V
Zero Gate Voltage Drain Current
On-State Drain Current
b
I
DSS
I
D(on)
V
DS
= 22.4 V, V
GS
= 0 V, T
J
= 55_C
V
DS
w
5 V, V
GS
= 5 V
V
GS
= 4.5 V, I
D
= 4.6 A
Drain-Source On-State Resistance
b
r
DS(on)
V
GS
= 3.0 V, I
D
= 4.3 A
V
GS
= 2.5 V, I
D
= 4.1 A
Forward Transconductance
b
Diode Forward Voltage
b
g
fs
V
SD
V
DS
= 10 V, I
D
= 4.6 A
I
S
= 1.25 A, V
GS
= 0 V
10
0.026
0.029
0.031
18
0.7
1.1
0.033
0.038
0.042
S
V
W
0.5
"1
"10
1
5
V
mA
mA
mA
m
A
Symbol
Test Condition
Min
Typ
Max
Unit
Dynamic
a
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
V
DD
= 10 V, R
L
= 10
W
I
D
^
1 A, V
GEN
= 4.5 V, R
G
= 6
W
V
DS
= 10 V, V
GS
= 4.5 V, I
D
= 4.6 A
14
2.1
4.2
0.55
2.0
7.0
4.5
1.0
4.0
12
8
ms
m
20
nC
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width
v
300
ms,
duty cycle
v
2%.
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Gate-Current vs. Gate-Source Voltage
8
10,000
1,000
I
GSS
- Gate Current (mA)
6
I
GSS
- Gate Current (
mA)
100
10
1
0.1
T
J
= 25_C
0.01
0
0
4
8
12
16
0.001
0
2
4
6
8
10
12
14
Gate Current vs. Gate-Source Voltage
4
T
J
= 150_C
2
V
GS
- Gate-to-Source Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Document Number: 70814
S-59522—Rev. C, 30-Nov-98
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Si6924EDQ
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Output Characteristics
20
V
GS
= 5 thru 2,5 V
16
I
D
- Drain Current (A)
2V
I
D
- Drain Current (A)
16
20
Transfer Characteristics
12
12
8
8
T
C
= 125_C
4
25_C
-55
_C
4
1.5 V
1V
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.0
0.5
1.0
1.5
2.0
2.5
V
DS
- Drain-to-Source Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
On-Resistance vs. Drain Current
0.05
1200
Capacitance
r
DS(on)
- On-Resistance (
W
)
V
GS
= 2.5 V
0.03
C - Capacitance (pF)
0.04
900
C
iss
600
C
oss
300
C
rss
V
GS
= 3 V
0.02
V
GS
= 4.5 V
0.01
0
4
8
12
16
20
0
0
4
8
12
16
20
24
28
I
D
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
Gate Charge
4.5
V
GS
- Gate-to-Source Voltage (V)
V
DS
= 10 V
I
D
= 4.6 A
1.8
On-Resistance vs. Junction Temperature
V
GS
= 4.5 V
I
D
= 4.6 A
r
DS(on)
- On-Resistance (
W)
(Normalized)
8
12
16
3.6
1.6
1.4
2.7
1.2
1.8
1.0
0.9
0.8
0.0
0
4
0.6
-50
-25
0
25
50
75
100
125
150
Q
g
- Total Gate Charge (nC)
T
J
- Junction Temperature (_C)
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Document Number: 70814
S-59522—Rev. C, 30-Nov-98
Si6924EDQ
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Source-Drain Diode Forward Voltage
20
0.08
On-Resistance vs. Gate-to-Source Voltage
I
S
- Source Current (A)
10
T
J
= 150_C
r
DS(on)
- On-Resistance (
W
)
0.06
I
D
= 4.6 A
0.04
T
J
= 25_C
0.02
1
0
0.4
0.6
0.8
1.0
1.2
0.00
0
1
2
3
4
5
V
SD
- Source-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Threshold Voltage
0.2
I
D
= 250
mA
30
25
Single Pulse Power
0.1
V
GS(th)
Variance (V)
-0.0
Power (W)
20
-0.1
15
-0.2
10
-0.3
5
0
-25
0
25
50
75
100
125
150
0.01
0.1
1
Time (sec)
10
30
T
J
- Temperature (_C)
-0.4
-50
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
0.05
P
DM
t
1
t
2
1. Duty Cycle, D =
t
1
t
2
0.02
Single Pulse
0.01
10
- 4
10
- 3
10
- 2
10
- 1
1
2. Per Unit Base = R
thJA
=
115
_C/W
3. T
JM
- T
A
= P
DM
Z
thJA(t)
4. Surface Mounted
10
100
600
Square Wave Pulse Duration (sec)
Document Number: 70814
S-59522—Rev. C, 30-Nov-98
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