Continuous Source Current (MOSFET Diode Conduction)
a
Average Foward Current (Schottky)
Pulsed Foward Current (Schottky)
Maximum Power Dissipation (MOSFET)
a
Maximum Power Dissipation (Schottky)
a
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak
Temperature)
b, c
T
A
= 25_C
T
A
= 85_C
T
A
= 25_C
T
A
= 85_C
T
J
, T
stg
P
D
T
A
= 25_C
T
A
= 85_C
Symbol
V
DS
V
KA
V
GS
I
D
I
DM
I
S
I
F
I
FM
5 sec
20
20
"8
5.9
4.2
20
1.8
1.0
7
2.1
1.1
1.9
1.0
Steady State
Unit
V
4.4
3.1
0.9
A
1.1
0.6
1.1
0.56
−55
to 150
260
_C
W
Notes
a. Surface Mounted on 1” x 1” FR4 Board.
b. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation
process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder intercon-
nection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 72234
S-32420—Rev. B, 24-Nov-03
www.vishay.com
1
Si5856DC
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
t
v
5 sec
Junction-to-Ambient
a
J
ti t A bi t
Steady St t
St d State
New Product
Device
MOSFET
Schottky
MOSFET
Schottky
MOSFET
Schottky
Symbol
Typical
50
54
Maximum
60
65
110
115
40
40
Unit
R
thJA
90
95
_C/W
Junction-to-Foot
Junction to Foot
Notes
a. Surface Mounted on 1” x 1” FR4 Board.
Steady State
R
thJF
30
30
MOSFET SPECIFICATIONS (T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
V
GS(th)
I
GSS
I
DSS
I
D(on)
V
DS
= V
GS
, I
D
= 250
mA
V
DS
= 0 V, V
GS
=
"8
V
V
DS
= 20 V, V
GS
= 0 V
V
DS
= 20 V, V
GS
= 0 V, T
J
= 85_C
V
DS
w
5 V, V
GS
= 4.5 V
V
GS
= 4.5 V, I
D
= 4.4 A
Drain-Source On-State Resistance
a
Forward Transconductance
a
Diode Forward Voltage
a
r
DS(on)
g
fs
V
SD
V
GS
= 2.5 V, I
D
= 4.1 A
V
GS
= 1.8 V, I
D
= 1.9 A
V
DS
= 10 V, I
D
= 4.4 A
I
S
= 1.0 A, V
GS
= 0 V
20
0.032
0.036
0.042
22
0.8
1.2
0.040
0.045
0.052
S
V
W
0.4
1.0
"100
1
5
V
nA
mA
A
Symbol
Test Condition
Min
Typ
Max
Unit
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
t
rr
I
F
= 0.9 A, di/dt = 100 A/ms
V
DD
= 10 V, R
L
= 10
W
I
D
^
1 A, V
GEN
= 4.5 V, R
G
= 6
W
V
DS
= 10 V, V
GS
= 4.5 V, I
D
= 4.4 A
5
0.85
1
20
36
30
12
45
30
55
45
20
90
ns
7.5
nC
Notes
a. Pulse test; pulse width
v
300
ms,
duty cycle
v
2%,
b. Guaranteed by design, not subject to production testing.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
