SN54/74LS323
8-BIT SHIFT/STORAGE REGISTER
WITH 3-STATE OUTPUTS
The SN54 / 74LS323 is an 8-Bit Universal Shift / Storage Register with
3-state outputs. Its function is similar to the SN54 / 74LS299 with the exception
of Synchronous Reset. Parallel load inputs and flip-flop outputs are
multiplexed to minimize pin count. Separate inputs and outputs are provided
for flip-flops Q0 and Q7 to allow easy cascading.
Four operation modes are possible: hold (store), shift left, shift right, and
parallel load. All modes are activated on the LOW-to-HIGH transition of the
Clock.
8-BIT SHIFT/STORAGE REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
•
Common I/O for Reduced Pin Count
•
Four Operation Modes: Shift Left, Shift Right, Parallel Load and Store
•
Separate Continuous Inputs and Outputs from Q0 and Q7 Allow Easy
•
•
•
•
Cascading
Fully Synchronous Reset
3-State Outputs for Bus Oriented Applications
Input Clamp Diodes Limit High-Speed Termination Effects
ESD > 3500 Volts
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
N SUFFIX
PLASTIC
CASE 738-03
1
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC S1
20 19
DS7 Q7
18
17
I/O7 I/O5 I/O3 I/O1 CP
16 15 14 13 12
DS0
11
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
20
1
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
1
S0
8
2
3
4
5
6
7
OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0
9
10
SR GND
PIN NAMES
HIGH
CP
DS0
DS7
I/On
OE1, OE2
Q0, Q7
S0, S1
SR
Clock Pulse (active positive going edge) Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Parallel Data Input or
Parallel Output (3-State) (Note c)
3-State Output Enable (active LOW) Inputs
Serial Outputs (Note b)
Mode Select Inputs
Synchronous Reset (active LOW) Input
LOADING
(Note a)
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
15 (7.5) U.L.
0.25 U.L.
5 (2.5) U.L.
0.25 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
65 (25) U.L.
0.5 U.L.
10 U.L.
1 U.L.
0.5 U.L.
NOTES:
a) 1 TTL LOAD = 40
µA
HIGH/1.6 mA LOW.
b) The output LOW drive factor is 2.5 U.L for Military (54) and 5 U.L. for Commercial Temperature Ranges.
c) The output LOW drive factor is 7.5 U.L for Military (54) and 15 U.L. for Commercial Temperature Ranges.
The output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial Temperature Ranges.
FAST AND LS TTL DATA
5-1
SN54/74LS323
S1
19
S0
1
LOGIC DIAGRAM
18
DS7
DS0
SR
12
11
9
CP
Q0
8
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
17
Q7
OE1
OE2
2
3
7
13
6
14
5
15
4
16
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
FUNCTIONAL DESCRIPTION
The logic diagram and truth table indicate the functional
characteristics of the SN54/74LS323 Universal Shift/Storage
Register. This device is similar in operation to the
SN54/74LS299 except for synchronous reset. A partial list of
the common features are described below:
1. They use eight D-type edge-triggered flip-flops that re-
spond only to the LOW-to-HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control (S0, S1) and data inputs (DS0, DS7, I/O0–I/O7) may
be stable at least a setup time prior to the positive transition
of the Clock Pulse.
2. When S0 = S1 = 1, I/O0–I/O7 are parallel inputs to flip-flops
Q0–Q7 respectively, and the outputs of Q0–Q7 are in the
high impedance state regardless of the state of OE1 or
OE2.
An important unique feature of the SN54/74LS323 is a fully
Synchronous Reset that requires only to be stable at least one
setup time prior to the positive transition of the Clock Pulse.
TRUTH TABLE
INPUTS
SR
L
L
L
L
L
H
H
H
H
H
H
H
H
S1
X
X
H
L
X
L
L
H
H
H
L
L
L
S0
X
X
H
X
L
H
H
L
L
H
L
L
L
OE1
H
X
X
L
L
X
L
X
L
X
H
X
L
OE2
X
H
X
L
L
X
L
X
L
X
X
H
L
X
X
X
CP
DS0
X
X
X
X
X
D
D
X
X
X
X
X
X
DS7
X
X
X
X
X
X
X
D
D
X
X
X
X
Synchronous Reset; Q0 = Q7 = LOW
I/O voltage undetermined
Synchronous Reset; Q0 = Q7 = LOW
I/O voltage LOW
Shift Right; D Q0; Q0 Q1; etc.
Shift Right; D Q0 & I/O0; Q0 Q1 & I/O1; etc.
Shift Left; D Q7; Q7 Q6; etc.
Shift Left; D Q7 & I/O7; Q7 Q6 & I/O6; etc.
Parallel Load I/On Qn
Hold; I/O Voltage Undetermined
Hold; I/On = Qn
RESPONSE
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
FAST AND LS TTL DATA
5-2
SN54/74LS323
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Output Current — High
Output Current — Low
Q0, Q7
Q0, Q7
Q0, Q7
I/O0 – I/O7
I/O0 – I/O7
I/O0 – I/O7
I/O0 – I/O7
Parameter
54
74
54
74
54, 74
54
74
54
74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
– 1.0
– 2.6
12
24
Unit
V
°C
mA
mA
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
Output HIGH Voltage
I/O0 – I/O7
Output HIGH Voltage
Q0, Q7
Output LOW Voltage
I/O0 – I/O7
Output LOW Voltage
Q0 – Q7
Output Off Current HIGH
I/O0 – I/O7
Output Off Current LOW
I/O0 – I/O7
Others
S0, S1,
I/O0 – I/O7
IIH
Input HIGH Current
Others
S0, S1
I/O0 – I/O7
Input LOW Current
IIL
IOS
Short Circuit Current
(Note 1)
Power Supply Current
Others
S0, S1
Qo, Q7
I/O0 – I/O7
– 20
– 30
54
74
54
74
54, 74
74
54, 74
74
2.4
2.4
2.5
2.7
– 0.65
3.2
3.1
3.4
3.4
0.25
0.35
0.4
0.5
0.4
0.5
40
– 400
20
40
0.1
0.2
0.1
– 0.4
– 0.8
–100
–130
53
0.8
– 1.5
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
VCC = MAX
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 5.5 V
VCC = MAX, VIN = 2.7 V
VCC = MIN, IOH = MAX
IOL = 12 mA
IOL = 24 mA
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MIN, IOH = MAX
Min
2.0
0.7
V
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VOH
VOL
VOL
IOZH
IOZL
VCC = MAX, VOUT = 2.7 V
VCC = MAX, VOUT = 0.4 V
ICC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-3
SN54/74LS323
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
fMAX
tPHL
tPLH
tPHL
tPLH
tPZH
tPZL
tPHZ
tPLZ
Parameter
Maximum Clock Frequency
Propagation Delay, Clock
to Q0 or Q7
Propagation Delay, Clock
to I/O0 – I/O7
Output Enable Time
Output Disable Time
Min
25
Typ
35
26
22
25
17
14
20
10
10
39
33
39
25
21
30
15
15
Max
Unit
MHz
ns
ns
ns
ns
CL = 45 pF,
RL = 667
Ω
CL = 15 pF
Test Conditions
CL = 5.0 pF
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tW
tW
tW
ts
ts
th
th
trec
Parameter
Clock Pulse Width HIGH
Clock Pulse Width LOW
Clear Pulse Width LOW
Data Setup Time
Select Setup Time
Data Hold Time
Select Hold Time
Recovery Time
Min
25
15
20
20
35
0
10
20
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
FAST AND LS TTL DATA
5-4
SN54/74LS323
3-STATE WAVEFORMS
VIN
tPHL
1.3 V
VOUT
1.3 V
tPLH
1.3 V
1.3 V
tPHL
1.3 V
VIN
1.3 V
tPLH
1.3 V
VOUT
1.3 V
Figure 1
Figure 2
VE
1.5 V
VE
VOUT
tPZL
1.5 V
0.5 V
1.5 V
tPLZ
≈
1.5 V
VOL
VE
1.5 V
VE
tPZH
1.5 V
VOUT
tPHZ
1.5 V
≥
VOH
≈
1.5 V
0.5 V
Figure 3
Figure 4
AC LOAD CIRCUIT
VCC
RL
SW1
SWITCH POSITIONS
SYMBOL
tPZH
SW1
Open
Closed
Closed
Closed
SW2
Closed
Open
Closed
Closed
TO OUTPUT
UNDER TEST
tPZL
tPLZ
tPHZ
5 kΩ
CL*
SW2
* Includes Jig and Probe Capacitance.
Figure 5
FAST AND LS TTL DATA
5-5
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