P REL I MIN AR Y
LM3S316 Microcontroller
D A TA S H E E T
DS-LM3S31 6-04
Co pyrigh t © 200 7 Lumin ary Micro, In c.
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Preliminary
April 27, 2007
LM3S316 Data Sheet
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 18
About This Document..................................................................................................................... 20
Audience........................................................................................................................................................... 20
About This Manual............................................................................................................................................ 20
Related Documents .......................................................................................................................................... 20
Documentation Conventions............................................................................................................................. 20
1.
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.5
Architectural Overview ....................................................................................................... 23
Product Features ................................................................................................................................. 23
Target Applications .............................................................................................................................. 27
High-Level Block Diagram ................................................................................................................... 28
Functional Overview ............................................................................................................................ 29
ARM Cortex™-M3 ............................................................................................................................... 29
Motor Control Peripherals .................................................................................................................... 29
Analog Peripherals .............................................................................................................................. 30
Serial Communications Peripherals..................................................................................................... 30
System Peripherals.............................................................................................................................. 31
Memory Peripherals............................................................................................................................. 32
Additional Features .............................................................................................................................. 33
Hardware Details ................................................................................................................................. 33
System Block Diagram ........................................................................................................................ 34
2.
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core........................................................................................ 35
Block Diagram ..................................................................................................................................... 36
Functional Description ......................................................................................................................... 36
Serial Wire and JTAG Debug .............................................................................................................. 36
Embedded Trace Macrocell (ETM) ...................................................................................................... 37
Trace Port Interface Unit (TPIU) .......................................................................................................... 37
ROM Table .......................................................................................................................................... 37
Memory Protection Unit (MPU) ............................................................................................................ 37
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 37
3.
4.
5.
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ........................................................................................................................ 43
Interrupts ............................................................................................................................. 45
JTAG Interface .................................................................................................................... 48
Block Diagram ..................................................................................................................................... 49
Functional Description ......................................................................................................................... 49
JTAG Interface Pins............................................................................................................................. 50
JTAG TAP Controller ........................................................................................................................... 51
Shift Registers ..................................................................................................................................... 52
Operational Considerations ................................................................................................................. 52
Initialization and Configuration............................................................................................................. 53
Register Descriptions........................................................................................................................... 54
Instruction Register (IR) ....................................................................................................................... 54
Data Registers ..................................................................................................................................... 56
6.
6.1
6.1.1
System Control.................................................................................................................... 58
Functional Description ......................................................................................................................... 58
Device Identification............................................................................................................................. 58
April 27, 2007
Preliminary
3
Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Reset Control ....................................................................................................................................... 58
Power Control ...................................................................................................................................... 61
Clock Control ....................................................................................................................................... 61
System Control .................................................................................................................................... 63
Initialization and Configuration............................................................................................................. 64
Register Map ....................................................................................................................................... 64
Register Descriptions........................................................................................................................... 65
7.
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
Internal Memory ................................................................................................................ 100
Block Diagram ................................................................................................................................... 100
Functional Description ....................................................................................................................... 100
SRAM Memory .................................................................................................................................. 100
Flash Memory .................................................................................................................................... 101
Initialization and Configuration........................................................................................................... 103
Changing Flash Protection Bits ......................................................................................................... 103
Flash Programming ........................................................................................................................... 104
Register Map ..................................................................................................................................... 104
Register Descriptions......................................................................................................................... 105
8.
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5
General-Purpose Input/Outputs (GPIOs) ........................................................................ 117
Block Diagram ................................................................................................................................... 118
Functional Description ....................................................................................................................... 118
Data Register Operation .................................................................................................................... 119
Data Direction .................................................................................................................................... 120
Interrupt Operation............................................................................................................................. 120
Mode Control ..................................................................................................................................... 121
Pad Configuration .............................................................................................................................. 121
Identification....................................................................................................................................... 121
Initialization and Configuration........................................................................................................... 121
Register Map ..................................................................................................................................... 123
Register Descriptions......................................................................................................................... 124
9.
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers .................................................................................................. 155
Block Diagram ................................................................................................................................... 156
Functional Description ....................................................................................................................... 156
GPTM Reset Conditions .................................................................................................................... 156
32-Bit Timer Operating Modes........................................................................................................... 156
16-Bit Timer Operating Modes........................................................................................................... 158
Initialization and Configuration........................................................................................................... 162
32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 162
32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 163
16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 163
16-Bit Input Edge Count Mode .......................................................................................................... 163
16-Bit Input Edge Timing Mode ......................................................................................................... 164
16-Bit PWM Mode.............................................................................................................................. 164
Register Map ..................................................................................................................................... 165
Register Descriptions......................................................................................................................... 166
10.
10.1
10.2
10.3
Watchdog Timer ................................................................................................................ 187
Block Diagram ................................................................................................................................... 187
Functional Description ....................................................................................................................... 188
Initialization and Configuration........................................................................................................... 188
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Preliminary
April 27, 2007
LM3S316 Data Sheet
10.4
10.5
Register Map ..................................................................................................................................... 188
Register Descriptions......................................................................................................................... 189
11.
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.3.1
11.3.2
11.4
11.5
Analog-to-Digital Converter (ADC) .................................................................................. 210
Block Diagram ................................................................................................................................... 211
Functional Description ....................................................................................................................... 211
Sample Sequencers .......................................................................................................................... 211
Module Control .................................................................................................................................. 212
Hardware Sample Averaging Circuit.................................................................................................. 213
Analog-to-Digital Converter ............................................................................................................... 213
Test Modes ........................................................................................................................................ 213
Internal Temperature Sensor ............................................................................................................. 213
Initialization and Configuration........................................................................................................... 213
Module Initialization ........................................................................................................................... 214
Sample Sequencer Configuration ...................................................................................................... 214
Register Map ..................................................................................................................................... 214
Register Descriptions......................................................................................................................... 215
12.
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.3
12.4
12.5
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 240
Block Diagram ................................................................................................................................... 241
Functional Description ....................................................................................................................... 241
Transmit/Receive Logic ..................................................................................................................... 241
Baud-Rate Generation ....................................................................................................................... 242
Data Transmission ............................................................................................................................. 243
FIFO Operation .................................................................................................................................. 243
Interrupts............................................................................................................................................ 243
Loopback Operation .......................................................................................................................... 244
Initialization and Configuration........................................................................................................... 244
Register Map ..................................................................................................................................... 245
Register Descriptions......................................................................................................................... 246
13.
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.4
13.5
Synchronous Serial Interface (SSI) ................................................................................. 276
Block Diagram ................................................................................................................................... 276
Functional Description ....................................................................................................................... 277
Bit Rate Generation ........................................................................................................................... 277
FIFO Operation .................................................................................................................................. 277
Interrupts............................................................................................................................................ 277
Frame Formats .................................................................................................................................. 278
Initialization and Configuration........................................................................................................... 285
Register Map ..................................................................................................................................... 286
Register Descriptions......................................................................................................................... 287
14.
14.1
14.2
14.2.1
14.2.2
14.3
14.4
14.5
14.6
Inter-Integrated Circuit (I2C) Interface ............................................................................ 311
Block Diagram ................................................................................................................................... 311
Functional Description ....................................................................................................................... 311
I
2
C Bus Functional Overview ............................................................................................................. 312
Available Speed Modes ..................................................................................................................... 321
Initialization and Configuration........................................................................................................... 322
Register Map ..................................................................................................................................... 323
Register Descriptions (I2C Master).................................................................................................... 323
Register Descriptions (I2C Slave)...................................................................................................... 337
April 27, 2007
Preliminary
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