MX10EXA
Major Difference
Feature
Product
FLASH
(K BYTES)
RAM
(BYTES)
BIT
(CPU BUS)
Package
MX10EXAQC
MX10EXAUC
MX10EXAQCG
MX10EXAUCG
64 K
2048
16
44 PLCC
40 LQFP
P/N:PM0625
Specifications subject to change without notice, contact your sales representatives for the most update information.
REV. 1.0, JUL. 01, 2005
1
MX10EXA
XA 16-bit Microcontroller Family
64K Flash/2K RAM, Watchdog, 2UARTs
FEATURE
• 4.5V to 5.5V
• 64K bytes of on-chip Flash program memory with In-
System Programming capability
• Five Flash blocks = two 8k byte blocks and three 16k
byte blocks
• Single supply voltage In-System Programming of the
Flash memory, (VPP=VDD or VPP=12V if desired)
• Boot ROM contains low level Flash programming
routines for In-Application Programming and a default
serial loader using the UART
• 2048 bytes of on-chip data RAM
• Supports off-chip program and data addressing up to 1
megabyte (20 address lines)
• Three standard counter/timers with enhanced features
All timers have a toggle output capability
• Watchdog timer
• Two enhanced UARTs with independent baud rates
• Seven software interrupts
• Four 8-bit I/O ports, with 4 programmable output
configurations for each pin
• 30 MHz operating frequency at 5V
• Power saving operating modes: Idle and Power-
Down.Wake-Up from power-down via an external inter-
rupt is supported.
• 44-pin PLCC (MX10EXAQC) Commercial grade
• 44-pin LQFP (MX10EXAUC) Commercial grade
• 44-pin PLCC (MX10EXAQI) Industrial grade
• 44-pin LQFP (MX10EXAUI) Industrial grade
GENERAL DESCRIPTION
The MX10EXA is a member of Philips’ 80C51 XA
(eXtended Architecture) family of high performance 16-
bit single-chip microcontrollers.
The MX10EXA contains 64k bytes of Flash program
memory, and provides three general purpose timers/
counters, a watchdog timer, dual UARTs, and four gen-
eral purpose I/O ports with programmable output con-
figurations.
1
A default serial loader program in the Boot ROM allows
In-System Programming (ISP) of the Flash memory with-
out the need for a loader in the Flash code. User pro-
grams may erase and reprogram the Flash memory at
will through the use of standard routines contained in
the Boot ROM (In-Application Programming).
PIN CONFIGURATIONS
P1.0/A0/WRH
P1.0/A0/WRH
P0.0/A4D0
P0.1/A5D1
P0.2/A6D2
P0.3/A7D3
P0.0/A4D0
P0.1/A5D1
P0.2/A6D2
P0.3/A7D3
P1.4/RxD1
P1.4/RxD1
44 PLCC
44 LQFP
P1.3/A3
P1.2/A2
P1.1/A1
P1.3/A3
P1.2/A2
P1.1/A1
V
DD
P1.5/TxD1
P1.6/T2
P1.7/T2EX
RST
P3.0/RxD0
NC
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1/BUSW
7
6
1
44
40
39
P0.4/A8D4
P0.5/A9D5
P0.6/A10D6
P0.7/A11D7
EA/VPP/WAIT
P1.5/TxD1
P1.6/T2
P1.7/T2EX
RST
P3.0/RxD0
NC
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1/BUSW
44
1
V
DD
V
SS
V
SS
34
33
P0.4/A8D4
P0.5/A9D5
P0.6/A10D6
P0.7/A11D7
EA/VPP/WAIT
12
MX10EXAQC
34
NC
ALE
PSEN
P2.7/A19D15
P2.6/A18D14
MX10EXAUC
NC
ALE
PSEN
P2.7/A19D15
P2.6/A18D14
17
18
V
SS
P3.6/WRL
P3.7/RD
XTAL2
XTAL1
23
V
DD
P2.0/A12D8
P2.1/A13D9
P2.2/A14D10
P2.3/A15D11
29
28
P2.4/A16D12
P2.5/A17D13
11
12
V
DD
P2.0/A12D8
P2.1/A13D9
P2.2/A14D10
P2.3/A15D11
P3.6/WRL
P3.7/RD
XTAL2
XTAL1
V
SS
23
22
P2.4/A16D12
P2.5/A17D13
P/N:PM0625
Specifications subject to change without notice, contact your sales representatives for the most update information.
REV. 1.0, JUL. 01, 2005
2
MX10EXA
BLOCK DIAGRAM
XA CPU Core
Program
Memory Bus
64K Bytes
FLASH
2048 Bytes
Static RAM
Port 0
Data
Bus
SFR
Bus
UART0
UART1
Timer 0,1
Port 1
Timer 2
Port 2
Port 3
Watchdog
Timer
LOGIC SYMBOL
VDD VSS
XTAL1
T2EX*
T2*
TxD1
RxD1
A3
A2
A1
A0/WRH
PORT 1
XTAL2
PORT 2
ALTERNATE FUNCTIONS
RxD0
TxD0
INT0
INT1
T0
T1/BUSW
WRL
RD
* NOT AVAILABLE ON 40-PIN DIP PACKAGE
P/N:PM0625
Specifications subject to change without notice, contact your sales representatives for the most update information.
REV. 1.0, JUL. 01, 2005
3
PORT 0
ADDRESS AND DATA BUS
RST
EA/WAIT
PSEN
ALE
PORT 3
ADDRESS
BUS
MX10EXA
PIN DESCRIPTIONS
MNEMONIC
V SS
V DD
P0.0-P0.7
PIN. NO.
PLCC
LQFP
1, 22
16,39
23, 44
17,38
43-36
37-30
TYPE
I
I
I/O
NAME AND FUNCTION
Ground:
0V reference.
Power Supply:
This is the power supply voltage for normal, idle, and
power down operation.
Port 0:
Port 0 is an 8-bit I/O port with a user-configurable output type.
Port 0 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. The operation of port 0 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
When the external program/data bus is used, Port 0 becomes the mul-
tiplexed low data/instruction byte and address lines 4 through 11.
Port 1:
Port 1 is an 8-bit I/O port with a user-configurable output type.
Port 1 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. The operation of port 1 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
Port 1 also provides special functions as described below.
A0/WRH:
Address bit 0 of the external address bus when the external
data bus is configured for an 8 bit width. When the external data bus is
configured for a 16 bit width, this pin becomes the high byte write
strobe.
A1:
Address bit 1 of the external address bus.
A2:
Address bit 2 of the external address bus.
A3:
Address bit 3 of the external address bus.
RxD1 (P1.4):
Receiver input for serial port 1.
TxD1 (P1.5):
Transmitter output for serial port 1.
T2 (P1.6):
Timer/counter 2 external count input/clockout.
T2EX (P1.7):
Timer/counter 2 reload/capture/direction control
Port 2:
Port 2 is an 8-bit I/O port with a user-configurable output type.
Port 2 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. The operation of port 2 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
When the external program/data bus is used in 16-bit mode, Port 2
becomes the multiplexed high data/instruction byte and address lines
12 through 19. When the external program/data bus is used in 8-bit
mode, the number of address lines that appear on port 2 is user pro-
grammable.
P1.0-P1.7
2-9
40-44,
1-3
I/O
2
40
O
P2.0-P2.7
3
4
5
6
7
8
9
24-31
41
42
43
44
1
2
3
18-25
O
O
O
I
O
I/O
I
I/O
P/N:PM0625
Specifications subject to change without notice, contact your sales representatives for the most update information.
REV. 1.0, JUL. 01, 2005
4
MX10EXA
MNEMONIC
P3.0-P3.7
PIN. NO.
PLCC
LQFP
11,13-19 5,7-13
TYPE
I/O
NAME AND FUNCTION
Port 3:
Port 3 is an 8-bit I/O port with a user configurable output type.
Port 3 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. the operation of port 3 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
Port 3 also provides various special functions as described below.
RxD0 (P3.0):
Receiver input for serial port 0.
TxD0 (P3.1):
Transmitter output for serial port 0.
INT0 (P3.2):
External interrupt 0 input.
INT1 (P3.3):
External interrupt 1 input.
T0 (P3.4):
Timer 0 external input, or timer 0 overflow output.
T1/BUSW (P3.5):
Timer 1 external input, or timer 1 overflow output.
The value on this pin is latched as the external reset input is released
and defines the default external data bus width (BUSW). 0 = 8-bit bus
and 1 = 16-bit bus.
WRL (P3.6):
External data memory low byte write strobe.
RD (P3.7):
External data memory read strobe.
Reset:
A low on this pin resets the microcontroller, causing I/O ports
and peripherals to take on their default states, and the processor to
begin execution at the address contained in the reset vector. Refer to
the section on Reset for details.
Address Latch Enable:
A high output on the ALE pin signals external
circuitry to latch the address portion of the multiplexed address/data
bus. A pulse on ALE occurs only when it is needed in order to process
a bus cycle.
Program Store Enable:
The read strobe for external program memory.
When the microcontroller accesses external program memory, PSEN
is driven low in order to enable memory devices. PSEN is only active
when external code accesses are performed.
External Access/Wait/Programming Supply Voltage:
The EA input
determines whether the internal program memory of the microcontroller
is used for code execution. The value on the EA pin is latched as the
external reset input is released and applies during later execution. When
latched as a 0, external program memory is used exclusively, when
latched as a 1, internal program memory will be used up to its limit, and
external program memory used above that point. After reset is released,
this pin takes on the function of bus Wait input. If Wait is asserted high
during any external bus access, that cycle will be extended until Wait
is released. During EPROM programming, this pin is also the program-
ming supply voltage input.
Crystal 1:
Input to the inverting amplifier used in the oscillator circuit
and input to the internal clock generator circuits.
Crystal 2:
Output from the oscillator amplifier.
11
13
14
15
16
17
5
7
8
9
10
11
I
O
I
I
I/O
I/O
RST
18
19
10
12
13
4
O
O
I
ALE
33
27
I/O
PSEN
32
26
O
EA/WAIT
/VPP
35
29
I
XTAL1
XTAL2
21
20
15
14
I
O
P/N:PM0625
Specifications subject to change without notice, contact your sales representatives for the most update information.
REV. 1.0, JUL. 01, 2005
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
