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5962R0624501V9A: 产品描述D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, DIE-64; 产品类别逻辑逻辑; 文件大小422KB，共26页; 制造商Cobham PLC

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5962R0624501V9A概述

D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, DIE-64

5962R0624501V9A规格参数

参数名称	属性值
厂商名称	Cobham PLC
包装说明	DIE, DIE OR CHIP
Reach Compliance Code	unknow
系列	ACT
JESD-30 代码	R-XUUC-N64
负载电容（CL）	50 pF
逻辑集成电路类型	D FLIP-FLOP
最大频率@ Nom-Su	100000000 Hz
最大I（ol）	0.024 A
位数	8
功能数量	2
端子数量	64
最高工作温度	125 °C
最低工作温度	-55 °C
输出特性	3-STATE
输出极性	TRUE
封装主体材料	UNSPECIFIED
封装代码	DIE
封装等效代码	DIE OR CHIP
封装形状	RECTANGULAR
封装形式	UNCASED CHIP
电源	5 V
Prop。Delay @ Nom-Su	10 ns
传播延迟（tpd）	10 ns
认证状态	Qualified
筛选级别	MIL-PRF-38535 Class V
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	4.5 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	CMOS
温度等级	MILITARY
端子形式	NO LEAD
端子位置	UPPER
总剂量	100k Rad(Si) V
触发器类型	POSITIVE EDGE

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REVISIONS

LTR

DESCRIPTION

Technical change for I

DDQ

and ΔI

DDQ

in table I. - PHN

Add die requirements with appendix A. Correct low and high level bounce

noise test condition for subgroup in the table IA. Update boilerplate

paragraphs to current MIL-PRF-38535 requirements. - MAA

Update electrical test requirements in table IIA for group C and D. Update

radiation features in section 1.5 and table IB. Update boilerplate paragraphs to

current requirements of MIL-PRF-38535. - MAA

Add equivalent test circuits footnotes to figure 6. Delete class M requirements

per updated boilerplate paragraphs. - MAA

DATE (YR-MO-DA)

07-04-02

09-02-10

APPROVED

Thomas M. Hess

Charles F. Saffle

11-06-14

David J. Corbett

12-11-19

Thomas M. Hess

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Phu H. Nguyen

CHECKED BY

Charles F. Saffle

APPROVED BY

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

Thomas M. Hess

DRAWING APPROVAL DATE

07-01-24

AMSC N/A

REVISION LEVEL

SIZE

CAGE CODE

STANDARD

MICROCIRCUIT

DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

http://www.landandmaritime.dla.mil

MICROCIRCUIT, DIGITAL, RADIATION

HARDENED CMOS, 16-BIT D FLIP FLOP, TTL

COMPATIBLE INPUTS, AND THREE-STATE

OUTPUTS, MONOLITHIC SILICON

67268

5962-06245

SHEET 1 OF 25

DSCC FORM 2233

APR 97

5962-E041-13

1.3 Absolute maximum ratings. 1/

Supply voltage range (V

) .................................................................................................. -0.3 V to 6.0 V

Voltage on any pin during operation (V

I/O

) .......................................................................... -0.3 V to V

+ 0.3 V

Maximum DC input current (I

) ............................................................................................

±10

Maximum power dissipation (P

) ........................................................................................ 310 mW

Thermal resistance, junction to case (θ

): .......................................................................... 20°C/W

Storage temperature range (T

STG

) ....................................................................................... -65°C to 150°C

Maximum junction temperature (T

) .................................................................................... 175°C

1.4 Recommended operating conditions.

Supply voltage range (V

) ................................................................................................... 4.5 V to 5.5 V

Input voltage any pin (V

) ................................................................................................... 0 V to V

Maximum input rise or fall time (t

INRISE

, t

INFALL

) ...................................................................... 20 ns

Temperature range (T

) ........................................................................................................ -55°C to 125°C

1.5 Radiation features.

Maximum total dose available (dose rate = 50 – 300 rads(Si)/s) ............................................

Single event phenomena (SEP):

No Single Event Latchup (SEL) occurs at effective LET (see 4.4.4.5) ..................................

No Single Event Upset (SEU) occurs at effective LET (see 4.4.4.5) ....................................

Neutron fluence ......................................................................................................................

100 Krad(Si)

≤ 108 MeV-cm /mg 2/

≤ 95 MeV-cm /mg 2/

1 x 10 n/cm 2/

________

1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the

maximum levels may degrade performance and affect reliability.

Limits are guaranteed by design or process, but not production tested unless specified by the customer through the

purchase order or contract.

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-06245

SHEET

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICATION

MIL-PRF-38535 - Integrated Circuits Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-883 -

MIL-STD-1835 -

Test Method Standard Microcircuits.

Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 -

MIL-HDBK-780 -

List of Standard Microcircuit Drawings.

Standard Microcircuit Drawings.

(Copies of these documents are available online at

https://assist.dla.mil/quicksearch/

or from the Standardization Document

Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Non-Government publications. The following document form a part of this document to the extent specified herein. Unless

otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.

ASTM INTERNATIONAL (ASTM)

ASTM F1192- Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion

Irradiation of Semiconductor Devices.

(Copies of this document is available online at

http://www.astm.org/

or from ASTM International, P. O. Box C700, 100 Barr

Harbor Driver, West Conshohocken, PA 19428-2959).

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein.

3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Function table. The function table shall be as specified on figure 3.

3.2.4 Logic diagram. The logic diagram shall be as specified on figure 4.

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-06245

SHEET

3.2.5 Ground bounce waveforms and test circuit. The ground bounce waveforms and test circuit shall be as specified on

figure 5.

3.2.6 Switching waveform and test circuit. The switching waveform and test circuit shall be as specified on figure 6.

3.2.7 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document

revision level control and shall be made available to the preparing and acquiring activity upon request.

3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and post-irradiation parameter limits are as specified in table IA and shall apply over the

full case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table IA.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein. The certificate of compliance

submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the

manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall

be provided with each lot of microcircuits delivered to this drawing.

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-06245

SHEET

5962R0624501V9A相似产品对比

	5962R0624501V9A	5962R0624501VXC	5962R0624501QXC	5962R0624501QXA	5962R0624501Q9A	5962R0624501VXA
描述	D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, DIE-64	D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, 0.390 X 0.640 INCH, 0.025 PITCH, DFP-48	D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, 0.390 X 0.640 INCH, 0.025 PITCH, DFP-48	D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, 0.390 X 0.640 INCH, 0.025 PITCH, DFP-48	D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, DIE-64	D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, 0.390 X 0.640 INCH, 0.025 PITCH, DFP-48
包装说明	DIE, DIE OR CHIP	QFF, FL48,.4,25	QFF, FL48,.4,25	QFF, FL48,.4,25	DIE, DIE OR CHIP	QFF, FL48,.4,25
Reach Compliance Code	unknow	unknown	unknown	unknown	unknow	unknow
系列	ACT	ACT	ACT	ACT	ACT	ACT
JESD-30 代码	R-XUUC-N64	R-XDFP-F48	R-XDFP-F48	R-XDFP-F48	R-XUUC-N64	R-XDFP-F48
负载电容（CL）	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
逻辑集成电路类型	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
最大I（ol）	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A
位数	8	8	8	8	8	8
功能数量	2	2	2	2	2	2
端子数量	64	48	48	48	64	48
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
输出极性	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	DIE	QFF	QFF	QFF	DIE	QFF
封装等效代码	DIE OR CHIP	FL48,.4,25	FL48,.4,25	FL48,.4,25	DIE OR CHIP	FL48,.4,25
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	UNCASED CHIP	FLATPACK	FLATPACK	FLATPACK	UNCASED CHIP	FLATPACK
电源	5 V	5 V	5 V	5 V	5 V	5 V
传播延迟（tpd）	10 ns	10 ns	10 ns	10 ns	10 ns	10 ns
认证状态	Qualified	Qualified	Qualified	Qualified	Qualified	Qualified
筛选级别	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class V
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
端子形式	NO LEAD	FLAT	FLAT	FLAT	NO LEAD	FLAT
端子位置	UPPER	DUAL	DUAL	DUAL	UPPER	DUAL
总剂量	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V
触发器类型	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
厂商名称	Cobham PLC	Cobham PLC	-	-	Cobham PLC	Cobham PLC
长度	-	16.002 mm	16.002 mm	16.002 mm	-	16.002 mm
座面最大高度	-	2.667 mm	2.667 mm	2.667 mm	-	2.667 mm
端子节距	-	0.635 mm	0.635 mm	0.635 mm	-	0.635 mm
宽度	-	9.652 mm	9.652 mm	9.652 mm	-	9.652 mm

5962R0624501V9A

5962R0624501V9A概述

5962R0624501V9A规格参数

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5962R0624501V9A相似产品对比

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