HPL5331
3A Bus Termination Regulator
Features
•
•
•
•
Provide Bi-direction Current
- Sourcing or Sinking Current up to 3A
1.25V/0.9V Output for DDR I/II Applications
Fast Transient Response
High Output Accuracy
- ±20mV over Load, VOUT Offset and
Temperature
•
•
•
•
•
Adjustable Output Voltage by External Resistors
Current-Limit Protection
On-Chip Thermal Shutdown
Shutdown for Standby or Suspend Mode
Simple SOP-8, SOP-8-P with thermal pad,
TO-252- 5 and TO-263-5 Packages
General Description (Cont.)
On-chip thermal shutdown provides protection against
any combination of overload that would create ex-
cessive junction temperature. The output voltage of
HPL5331
track the voltage at VREF pin. A resistor
divider connected to VIN, GND and VREF pins is
used to provide a half voltage of VIN to VREF pin. In
addition, an external ceramic capacitor and an open-
drain transistor connected to VREF pin provides soft-
start and shutdown control respectively. Pulling and
holding the VREF to GND shuts off the output. The
output of HPL5331 will be high impedance after being
shut down by VREF or thermal shutdown function.
Pin Configuration
VIN
GND
Applications
•
•
•
DDR I/II SDRAM Termination
SSTL-2/3 Termination Voltage
Applications Requiring the Regulator with
Bi-direction 3A Current Capability
1
2
3
4
8
7
6
5
VCNTL
VCNTL
VCNTL
VCNTL
VOUT
VREF
VCNTL
GND
VIN
VREF
VOUT
TAB is VCNTL
SOP-8 (Top View)
VIN
TO-252-5 (Top View)
5
4
3
2
1
VOUT
VREF
VCNTL
GND
VIN
1
2
3
4
8
7
6
5
NC
NC
General Description
The HPL5331 linear regulator is designed to provide a
regulated voltage with bi-directional output current for
DDR-SDRAM termination. The HPL5331 integrates
two power transistors to source or sink current up to
3A. It also incorporate current-limit, thermal shutdown
and shutdown control functions into a single chip. Cur-
rent-limit circuit limits the short-circuit current.
GND
VREF
VOUT
TAB is VCNTL
VCNTL
NC
SOP-8-P (Top View)
NC = No internal connection
TO-263-5 (Top View)
= Thermal Pad
(connected to GND plane for better heat
dissipation)
Copyright HIPAC Semiconductor, Inc.
Rev. A.8 - Oct., 2003
1
www.hipacsemi.com
1
2
3
4
5
HPL5331
Ordering and Marking Information
HPL5331
Lead Free Code
Handling Code
Temp. Range
Package Code
Package Code
K : SOP-8
KA : SOP-8-P
U5 : TO-252-5
G5 : TO-263-5
Temp. Range
C : 0 to 70
o
C
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device Blank : Original Device
HPL5331KC-TR :
HPL5331KAC-TR :
HPL5331
XXXXX
XXXXX - Date Code
HPL5331U5C-TR :
HPL5331G5C-TR :
HPL5331
XXXXX
XXXXX - Date Code
Pin Description
PIN NAME
VIN
I/O
I
DESCRIPTION
Main power input pin. Connect this pin to a voltage source and an input
capacitor. The HPL5331 sources current to VOUT pin by controlling the upper
NPN pass transistor, providing a current path from VIN pin.
Power and signal ground. Connect this pin to system ground plane with shortest
traces. The HPL5331 sinks current from VOUT pin by controlling the lower NPN
pass transistor, providing a current path to GND pin. This pin is also the ground
path for internal control circuitry.
Power input pin for internal control circuitry.
V C NTL
Connect this pin to a voltage source,
providing a bias for the internal control circuitry. A bypass capacitor is usually
connected near this pin.
Reference voltage input and active-low shutdown control pin. Apply a voltage to
this pin as a reference voltage for the HPL5331. Connect this pin to a resistor
divider, between VIN and GND, and a capacitor for soft-start and filtering noise
C u rre n t
purposes. Applying and holding this pin low by an open-drain transistor to shut
Lim it
down the output.
Output pin of the regulator. Connect this pin to load. Output capacitors
connected this pin improves stability and transient response. The output voltage
tracks the reference voltage and is capable of sourcing or sinking current up to
3A.
GND
O
VCNTL
I
VREF
I
VOUT
O
Block Diagram
V C NTL
V IN
V RE F
V o lt ag e
R e g ulat io n
Th erm a l
L im it
C u rre nt
L im it
V OUT
S h u td ow n
G ND
Copyright HIPAC Semiconductor, Inc.
Rev. A.8 - Oct., 2003
2
www.hipacsemi.com
HPL5331
Absolute Maximum Ratings
Symbol
V
CNTL
V
IN
P
D
T
J
T
STG
T
SDR
V
ESD
Parameter
VCNTL Supply Voltage, VCNTL to GND
VIN Supply Voltage, VIN to GND
Power Dissipation
Junction Temperature
Storage Temperature
Soldering Temperature, 10 Seconds
Minimum ESD Rating (Human Body Mode)
Rating
-0.2 ~ 7
-0.2 ~ 3.9
Internally Limited
150
-65 ~ 150
300
±3
Unit
V
V
W
o
o
o
C
C
C
kV
Thermal Characteristics
Symbol
θ
JA
Parameter
Thermal Resistance in Free Air
SOP-8
SOP-8-P
TO-252-5
TO-263-5
Rating
160
80
80
50
Unit
°C/W
Recommended Operating Conditions
Symbol
V
CNTL
V
IN
V
REF
I
OUT
T
J
Parameter
VCNTL Supply Voltage
VIN Supply Voltage
VREF Input Voltage
VOUT Output Current (Note1, 2)
Junction Temperature
Range
3.1 ~ 6V
1.6 ~ 3.5
0.8 ~ 1.75
-3 ~ +3
0 ~ 125
Unit
V
V
V
A
o
C
Note1 : The symbol “+” means the VOUT sources current to load; the symbol “-“ means the VOUT sinks
current to GND.
Note2 : The max. I
OUT
varies with the T
J
. Please refer to the typical characteristics.
Copyright HIPAC Semiconductor, Inc.
Rev. A.8 - Oct., 2003
3
www.hipacsemi.com
HPL5331
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over, V
CNTL
=3.3V, V
IN
=2.5V/1.8V,
V
REF
=0.5V
IN
and T
J
= 0 to 125°C, unless otherwise specified. Typical values refer to T
J
=25°C.
Symbol
Output Voltage
V
OUT
VOUT Output Voltage
System Accuracy
V
OS
VOUT Offset Voltage
(V
OUT
–V
REF
)
Load Regulation
Protection
Sourcing Current
(V
IN
=2.5V)
Sinking Current
(V
IN
=2.5V)
Sourcing Current
(V
IN
=1.8V)
Sinking Current
(V
IN
=1.8V)
T
J
=25°C
T
J
=125°C
T
J
=25°C
T
J
=125°C
T
J
=25°C
T
J
=125°C
T
J
=25°C
T
J
=125°C
+3.3
-3.3
+2.9
-2.9
+3.6
+3.1
-3.6
-3.1
+3.2
+2.6
-3.2
-2.6
150
40
2
4.5
50
2.6
150
20
0.2
500
40
nA
µA
V
6
110
mA
I
OUT
=0A
Over temperature, VOUT offset, and
load regulation
I
OUT
=+10mA
I
OUT
=-10mA
I
OUT
=+10mA to +3A
I
OUT
= -10mA to -3A
-6
V
REF
-20
-14
-9
2
-3
7
12
8
20
V
mV
mV
mV
Parameter
Test Conditions
HPL5331
Min
Typ
Max
Unit
I
LIM
Current Limit
A
T
SD
Thermal Shutdown
Rising T
J
Temperature
Thermal Shutdown Hysteresis
I
OUT
=0A
I
OUT
=±3A (Normal Operation),
V
CNTL
=5V
V
REF
=GND (Shutdown)
o
o
C
C
Input Current
I
CNTL
VCNTL Supply Current
I
VREF
V
REF
=1.25V/0.9V (Normal Operation)
VREF Bias Current
(The current flows out of VREF) V
REF
=GND (Shutdown)
Shutdown Threshold Voltage
Shutdown Control
0.35 0.65
Copyright HIPAC Semiconductor, Inc.
Rev. A.8 - Oct., 2003
4
www.hipacsemi.com
HPL5331
Typical Application Circuit
1. V
OUT
=1.25V/0.9V Application
V
C N TL
+3 .3 V
V
IN
+2 .5 V/1 .8 V
R
1
1k
C
IN
4 70 uF
Shu td o w n
Q
1
GN D
R
2
1k
V
R EF
C
SS
0 .1u F
C
C N TL
4 7u F
VIN
VC N TL
VR EF
GN D
VO U T
V
OU T
+1 .2 5 V/0.9 V
-3 ~+3 A
C
OU T
4 70 uF
GN D
C
OUT
: 470µF, ESR=25mΩ
R
1
, R2 : 1kΩ, 1%
Q1 : HPM2300 AC
Note : Since R
1
and R
2
are very small, the voltage offset
caused by the bias current of VREF can be ignore.
2. V
OUT
=1.4V Application
V
CNT L
+5V
V
IN
+2.8V
R
1
1k
C
IN
470
µ
F
R
2
1k
GND
V
RE F
C
SS
0.1
µ
F
C
CNT L
47
µ
F
C
O UT
470
µ
F
VIN
VC N TL
VR EF
GN D VOU T
V
OUT
+1.4V/
-3~+3 A
GND
Copyright HIPAC Semiconductor, Inc.
Rev. A.8 - Oct., 2003
5
www.hipacsemi.com
stm32/stm8
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