• Phase-locked loop (PLL) clock distribution for Double
Data Rate Synchronous DRAM applications
• 1:5 differential outputs
• External feedback pins (FBINT, FBINC) are used to
synchronize the outputs to the clock input
• SSCG: Spread Aware™ for electromagnetic
interference (EMI) reduction
• 28-pin TSSOP package
• Conforms to JEDEC DDR specifications
Functional Description
The CY2SSTV855 is a high-performance, very-low-skew,
very-low-jitter zero-delay buffer that distributes a differential
clock input pair (SSTL_2) to four differential (SSTL_2) pairs of
clock outputs and one differential pair of feedback clock
outputs. In support of low power requirements, when
power-down is HIGH, the outputs switch in phase and
frequency with the input clock. When power-down is LOW, all
outputs are disabled to a high-impedance state and the PLL is
shut down.
The device supports a low-frequency power-down mode.
When the input is < 20 MHz, the PLL is disabled and the
outputs are put in the Hi-Z state. When the input frequency is
> 20 MHz, the PLL and outputs are enabled.
When AVDD is tied to ground, the PLL is turned off and
bypassed with the input reference clock gated to the outputs.
The Cypress CY2SSTV855 is Spread Aware and supports
tracking of Spread Spectrum clock inputs to reduce EMI
Block Diagram
Pin Configuration
YT0
YC0
PWRDWN
AVDD
Powerdown
and test
logic
YT1
YC1
GND
YC0
YT0
VDDQ
GND
CLKINT
CLKINC
VDDQ
AVDD
AGND
VDDQ
YT1
YC1
GND
YT2
YC2
CLKINT
CLKINC
FBINT
FBINC
PLL
YT3
YC3
FBOUTT
FBOUTC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
YC3
YT3
VDDQ
PWRDWN
FBINT
FBINC
VDDQ
FBOUTC
FBOUTT
VDDQ
YT2
YC2
GND
28-pin TSSOP
CY2SSTV855
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 6
www.SpectraLinear.com
CY2SSTV855
Pin Definition
[1, 2]
Pin
6
7
22
23
3,12,17,26
2,13,16,27
19
Name
CLKINT
CLKINC
FBINC
FBINT
YT(0:3)
YC(0:3)
FBOUTT
I/O
I
I
I
I
O
O
O
Description
True Clock Input.
Low Voltage Differential True Clock Input.
Complementary Clock Input.
Low Voltage Differential Complementary Clock Input.
Feedback Complementary Clock Input.
Differential Input Connect to FBOUTC for
accessing the PLL.
Feedback True Clock Input.
Differential Input Connect to FBOUTT for accessing the
PLL.
True Clock Outputs.
Differential Outputs.
Complementary Clock Outputs.
Differential Outputs.
Feedback True Clock Output.
Differential Outputs. Connect to FBINT for normal
operation. A bypass delay capacitor at this output will control Input Reference/Output
Clocks phase relationships.
Feedback Complementary Clock Output.
Differential Outputs. Connect to FBINC for
normal operation. A bypass delay capacitor at this output will control Input
Reference/Output Clocks phase relationships.
Control input to turn device in the power-down mode.
2.5V Power Supply for Output Clock Buffers.2.5V
Nominal.
2.5V Power Supply for PLL.
2.5V Nominal.
Ground
Analog Ground.
2.5V Analog Ground.
connecting the feedback output to the feedback input the
propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge
thus producing a near zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs.
When AVDD is strapped LOW, the PLL is turned off and
bypassed for test purposes.
20
FBOUTC
O
24
4,8,11,18,21,25
9
1,5,14,15,28
10
PWRDWN
VDDQ
AVDD
GND
AGND
I
Zero-delay Buffer
When used as a zero-delay buffer the CY2SSTV855 will likely
be in a nested clock tree application. For these applications
the CY2SSTV855 offers a differential clock input pair as a PLL
reference. The CY2SSTV855 then can lock onto the reference
and translate with near zero delay to low-skew outputs. For
normal operation, the external feedback differential input,
FBINT/C, is connected to the feedback output, FBOUTT/C. By
Function Table
Inputs
AVDD
GND
GND
2.5V
2.5V
2.5V
PWRDWN
H
H
H
H
X
CLKINT
L
H
L
H
< 20 MHz
CLKINC
H
Outputs
YT(0:3)
L
H
L
H
Hi-Z
YC(0:3)
H
L
H
L
Hi-Z
FBOUTT
L
H
L
H
Hi-Z
FBOUTC
H
L
H
L
Hi-Z
PLL
BYPASSED/OFF
BYPASSED/OFF
On
On
Off
L
H
L
< 20 MHz
Notes:
1. PU = internal pull-up.
2. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Rev 1.0, November 21, 2006
Page 2 of 6
CY2SSTV855
Differential Parameter Measurement Information
CLKINT
CLKINC
FBINT
FBINC
t
( )
n
t
( )
n =
n =N
1
N
t
( )
n+1
t
( )
n
N (is large number of samples)
Figure 1. Static Phase Offset
CLKINT
CLKINC
FBINT
FBINC
td( )
t( )
td( )
td( )
t(
)
td( )
Figure 2. Dynamic Phase Offset
Y[0:3], FBOUTT
YC[0:3], FBOUTC
Y[0:3], FBOUTT
YC[0:3], FBOUTC
tsk(o)
Figure 3. Output Skew
Rev 1.0, November 21, 2006
Page 3 of 6
CY2SSTV855
Differential Parameter Measurement Information
(continued)
YT[0:3], FBOUTT
YC[0:3], FBOUTC
t
(hper_n)
1
f(o)
t
(hper_N+1)
t
jit(hper)
= t
hper(n)
- 1
2x fo
Figure 4. Half-period Jitter
YT[0:3], FBOUTT
YC[0:3], FBOUTC
t
c(n)
t
j
it(cc)
= t
c(n)
-t
c(n+1)
Figure 5. Cycle-to-cycle Jitter
t
c(n)
VDD
VDD
V D D /2
16pF
C LKT
60 O hm
VTR
R
T
= 120 O hm
C LKC
60 O hm
16pF
V D D /2
VCP
R e c e iv e r
Figure 6. Differential Signal Using Direct Termination Resistor
Rev 1.0, November 21, 2006
Page 4 of 6
CY2SSTV855
Absolute Maximum Conditions
[3]
Input Voltage Relative to V
SS
:............................... V
SS
– 0.3V
Input Voltage Relative to V
DDQ
or AV
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................ –65 C to + 150 C
Operating Temperature:................................ –40 C to +85 C
Maximum Power Supply: ................................................ 3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Electrical Specifications
(
AV
DD
= V
DDQ
= 2.5V ± 5%, T
A
= –40°C to +85°C)
[4]
Parameter
V
ID
V
IX
I
IN
I
OL
I
OH
V
OL
V
OH
V
OUT
V
OC
I
OZ
I
DDQ
I
DD
Cin
Description
Differential Input Voltage
[5]
Conditions
CLKINT, FBINT
Min.
0.36
(V
DDQ
/2) –
0.2
–10
26
–18
1.7
1.1
(V
DDQ
/2) –
0.2
Typ.
V
DDQ
/2
–
35
–32
–
–
–
V
DDQ
/2
Max.
V
DDQ
+ 0.6
(V
DDQ
/2) +
0.2
10
–
–
0.6
–
V
DDQ
– 0.4
(V
DDQ
/2) +
0.2
10
300
12
–
Unit
V
V
µA
mA
mA
V
V
V
V
µA
mA
mA
pF
Differential Input Crossing Voltage
[6]
CLKTIN, FBINT
Input Current
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing
[7]
Output Crossing Voltage
[8]
High-Impedance Output Current
Dynamic Supply Current
[9]
PLL Supply Current
Input Pin Capacitance
V
O
= GND or V
O
= V
DDQ
V
DDQ
= 170 MHz
AV
DD
only
V
IN
= 0V or V
IN
= V
DDQ
, CLKINT,
FBINT
V
DDQ
= 2.375V, V
OUT
= 1.2V
V
DDQ
= 2.375V, V
OUT
= 1V
V
DDQ
= 2.375V, I
OL
= 12 mA
V
DDQ
= 2.375V, I
OH
= –12 mA
–10
–
–
–
235
9
4
AC Electrical Specifications
(
AV
DD
= V
DDQ
= 2.5V±5%, T
A
= –40°C to +85°C)
[10, 11]
Parameter
f
CLK
t
DC
t
LOCK
t
SL(O)
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
CCJ
t
JITT(H-PER)
Description
Operating Clock Frequency
Input Clock Duty Cycle
[12]
Maximum PLL lock Time
Output Clocks Slew Rate
Output Enable Time (all outputs)
[13]
Output Disable Time (all outputs)
[13]
Cycle to Cycle Jitter
Half-period jitter
Conditions
AV
DD
= 2.5V
0.2V
Min.
60
40
Typ.
Max.
170
60
100
2
Unit
MHz
%
µs
V/ns
ns
ns
20% to 80% of VOD
1
30
10
f > 66 MHz
f > 66 MHz
–100
–100
100
100
ps
ps
Notes:
3.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the comple-
mentary input level.
6. Differential cross-point input voltage is expected to track V
DDQ
and is the voltage at which the differential signals must be crossing.
7. For load conditions see
Figure 6.
8. The value of V
OC
is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120 resistor. See
Figure 6.
9. All outputs switching loaded with 16 pF in 60 environment. See
Figure 6.
10. Parameters are guaranteed by design and characterization. Not 100% tested in production.
11. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a
downspread of –0.5%
12. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t
WH
/t
C
,
where the cycle time (t
C
) decreases as the frequency goes up.
13. Refers to transition of non-inverting output.
14. All differential input and output terminals are terminated with 120 /16 pF as shown in
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