Revision 13
ProASIC3E Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
High Capacity
• 600 k to 3 Million System Gates
• 108 to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Pro (Professional) I/O
•
•
•
•
•
•
•
•
•
•
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay
Schmitt Trigger Option on Single-Ended Inputs
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC
®
3E Family
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous Interfacing
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
Designed to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, Each with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Low Power
• Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous Operation
up to 350 MHz
• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available
with or without Debug
High-Performance Routing Hierarchy
•
•
•
•
•
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very-Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
ARM
®
Processor Support in ProASIC3E FPGAs
Table 1-1 • ProASIC3E Product Family
ProASIC3E Devices
Cortex-M1 Devices
1
System Gates
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Kbits
Secure (AES) ISP
CCCs with Integrated
VersaNet
Globals
3
I/O Banks
Maximum User I/Os
Package Pins
PQFP
FBGA
PLLs
2
600,000
13,824
108
24
1
Yes
6
18
8
270
PQ208
FG256, FG484
A3PE600
A3PE1500
M1A3PE1500
1,500,000
38,400
270
60
1
Yes
6
18
8
444
PQ208
FG484, FG676
A3PE3000
M1A3PE3000
3,000,000
75,264
504
112
1
Yes
6
18
8
620
PQ208
FG324
,
FG484, FG896
Notes:
1. Refer to the
Cortex-M1
product brief for more information.
2. The PQ208 package supports six CCCs and two PLLs.
3. Six chip (main) and three quadrant global networks are available.
4. For devices supporting lower densities, refer to the
ProASIC3 Flash Family FPGAs
datasheet.
January 2013
© 2013 Microsemi Corporation
I
ProASIC3E Flash Family FPGAs
I/Os Per Package
1
ProASIC3E Devices
Cortex-M1 Devices
2
A3PE600
A3PE1500
3
M1A3PE1500
I/O Types
Differential I/O Pairs
Differential I/O Pairs
Differential I/O Pairs
65
–
110
168
–
310
FG896
31 × 31
961
1.0
2.23
Status
Production
Production
Single-Ended I/O
1
Single-Ended I/O
1
Single-Ended I/O
1
147
–
221
341
–
620
FG676
27 × 27
729
1.0
2.23
A3PE3000
3
M1A3PE3000
Package
PQ208
FG256
FG324
FG484
FG676
FG896
147
165
–
270
–
–
65
79
–
135
–
–
147
–
–
280
444
–
65
–
–
139
222
–
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the
ProASIC3E FPGA Fabric User’s
Guide
to ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per
minibank (group of I/Os).
6. "G" indicates RoHS-compliant packages. Refer to the
"ProASIC3E Ordering Information" on page III
for the location of the "G"
in the part number.
Table 1-2 • ProASIC3E FPGAs Package Sizes Dimensions
Package
Length × Width (mm\mm)
Nominal Area (mm
2
)
Pitch (mm)
Height (mm)
PQ208
28 × 28
784
0.5
3.40
FG256
17 × 17
289
1.0
1.60
FG324
19 × 19
361
1.0
1.63
FG484
23 × 23
529
1.0
2.23
ProASIC3E Device Status
ProASIC3E Devices
A3PE600
A3PE1500
A3PE3000
Status
Production
Production
Production
M1A3PE1500
M1A3PE3000
M1 ProASIC3E Devices
II
R evis i o n 13
ProASIC3E Flash Family FPGAs
ProASIC3E Ordering Information
A3PE3000 _
1
FG
G
896
Y
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (–40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS-Compliant (Green) Packaging
Package Type
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
ProASIC3E Devices
A3PE600 = 600,000 System Gates
A3PE1500 = 1,500,000 System Gates
A3PE3000 = 3,000,000 System Gates
ProASIC3E Devices with Cortex-M1
M1A3PE1500 = 1,500,000 System Gates
M1A3PE3000 = 3,000,000 System Gates
R ev i si o n 1 3
III
ProASIC3E Flash Family FPGAs
Temperature Grade Offerings
Package
Cortex-M1 Devices
PQ208
FG256
FG324
FG484
FG676
FG896
C, I
C, I
–
C, I
–
–
A3PE600
A3PE1500
M1A3PE1500
C, I
–
–
C, I
C, I
–
A3PE3000
M1A3PE3000
C, I
–
C, I
C, I
–
C, I
Note:
C = Commercial temperature range: 0°C to 70°C ambient temperature
I = Industrial temperature range: –40°C to 85°C ambient temperature
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
1
I
2
Std.
–1
–2
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature
2. I = Industrial temperature range: –40°C to 85°C ambient temperature
References made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Microsemi SoC Products Group representative for device availability:
http://www.microsemi.com/soc/contact/default.aspx.
IV
Revision 13
ProASIC3E Flash Family FPGAs
Table of Contents
ProASIC3E Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ProASIC3E DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
Pin Descriptions and Packaging
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3-2
3-3
3-4
3-4
3-4
Package Pin Assignments
PQ208
FG256
FG324
FG484
FG676
FG896
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
R ev i si o n 1 3
V
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
