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5962D9317707VTC: 产品描述Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO; 产品类别存储存储; 文件大小2MB，共20页; 制造商Atmel (Microchip)

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5962D9317707VTC概述

Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO

5962D9317707VTC规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	Atmel (Microchip)
零件包装代码	DIP
包装说明	DIP, DIP28,.3
针数	28
Reach Compliance Code	compliant
ECCN代码	EAR99
最长访问时间	40 ns
其他特性	RETRANSMIT
最大时钟频率 (fCLK)	25 MHz
周期时间	30 ns
JESD-30 代码	R-XDIP-T28
JESD-609代码	e4
长度	27.94 mm
内存密度	147456 bit
内存集成电路类型	OTHER FIFO
内存宽度	9
功能数量	1
端子数量	28
字数	16384 words
字数代码	16000
工作模式	ASYNCHRONOUS
最高工作温度	125 °C
最低工作温度	-55 °C
组织	16KX9
可输出	NO
封装主体材料	UNSPECIFIED
封装代码	DIP
封装等效代码	DIP28,.3
封装形状	RECTANGULAR
封装形式	IN-LINE
并行/串行	PARALLEL
电源	5 V
认证状态	Qualified
筛选级别	MIL-PRF-38535 Class V
座面最大高度	3.94 mm
最大压摆率	0.11 mA
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	4.5 V
标称供电电压 (Vsup)	5 V
表面贴装	NO
技术	CMOS
温度等级	MILITARY
端子面层	Gold (Au)
端子形式	THROUGH-HOLE
端子节距	2.54 mm
端子位置	DUAL
总剂量	10k Rad(Si) V
宽度	7.62 mm
Base Number Matches	1

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Features

•

First-in First-out Dual Port Memory

16384 bits x 9 Organization

Fast Flag and Access Times: 15, 30 ns

Wide Temperature Range: - 55°C to + 125°C

Fully Expandable by Word Width or Depth

Asynchronous Read/Write Operations

Empty, Full and Half Flags in Single Device Mode

Retransmit Capability

Bi-directional Applications

Battery Back-up Operation: 2V Data Retention

TTL Compatible

Single 5V ± 10% Power Supply

No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm

Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019

Quality grades: QML Q and V with SMD 5962-93177 and ESCC with specification

9301/048

Rad. Tolerant

High Speed

16 Kb x 9

Parallel FIFO

M67206H

Description

The M67206H implements a first-in first-out algorithm, featuring asynchronous

read/write operations. The FULL and EMPTY flags prevent data overflow and under-

flow. The Expansion logic allows unlimited expansion in word size and depth with no

timing penalties. Twin address pointers automatically generate internal read and write

addresses, and no external address information is required. Address pointers are

automatically incremented with the write pin and read pin. The 9 bits wide data are

used in data communications applications where a parity bit for error checking is nec-

essary. The Retransmit pin resets the Read pointer to zero without affecting the write

pointer. This is very useful for retransmitting data when an error is detected in the

system.

Using an array of eight transistors (8T) memory cell, the M67206H combines an

extremely low standby supply current (typ = 0.1

µA)

with a fast access time at 15 ns

over the full temperature range. All versions offer battery backup data retention capa-

bility with a typical power consumption at less than 2

µW.

The M67206H is processed according to the methods of the latest revision of the MIL

PRF 38535 (Q and V) or ESCC 9000.

Rev. 4143J–AERO–04/07

Write Enable (W)

A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.

Data set-up and hold times must be maintained in the rise time of the leading edge of

the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any

current read operation.

Once half the memory is filled, and during the falling edge of the next write operation,

the Half-Full Flag (HF) will be set to low and remain in this state until the difference

between the write and read pointers is less than or equal to half of the total available

memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the

read operation.

To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-

tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,

allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is

blocked from W, so that external changes to W will have no effect on the full FIFO stack.

Read Enable (R)

A read cycle is initiated on the falling edge of the Read Enable (R) provided that the

Empty Flag (EF) is not set. The data is accessed on a first-in/first-out basis, not includ-

ing any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0

- Q8) will return to a high impedance state until the next Read operation. When all the

data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the

“final” read cycle, but inhibiting further read operations while the data outputs remain in

a high impedance state. Once a valid write operation has been completed, the Empty

Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO

stack is empty, the internal read pointer is blocked from R, so that external changes to R

will have no effect on the empty FIFO stack.

This pin is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to

ground to indicate that it is the first loaded (see Operating Modes). In the Single Device

Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-

necting the Expansion In (XI) to ground.

The M67206H can be set to retransmit data when the Retransmit Enable Control (RT)

input is pulsed low. A retransmit operation will set the internal read point to the first loca-

tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be

in the high state during retransmit. The retransmit feature is intended for use when a

number of writes are equal to or less than the depth of the FIFO has occurred since the

last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode

and will affect the Half-Full Flag (HF), in accordance with the relative locations of the

read and write pointers.

First Load/Retransmit

(FL/RT)

Expansion In (XI)

The XI input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an

operation in the single device mode. Expansion In (XI) is connected to Expansion Out

(XO) of the previous device in the Depth Expansion or Daisy Chain modes.

The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is

one location less than the read pointer, indicating that the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.

The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer

is equal to the write pointer, indicating that the device is empty.

Full Flag (FF)

Empty Flag (EF)

M67206H

4143J–AERO–04/07

5962D9317707VTC相似产品对比

	5962D9317707VTC	5962-9317707QNC	5962-9317707VTC	5962D9317707VNC	5962D9317708VTC	MM0-67206HV-15SV	MM067206HV-15-E	MMDP-67206HV-15-E
描述	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO
零件包装代码	DIP	DFP	DIP	DFP	DIP	DIE	DIE	DFP
包装说明	DIP, DIP28,.3	DFP, FL28,.4	DIP, DIP28,.3	DFP, FL28,.4	DIP, DIP28,.3	DIE,	DIE,	DFP,
Reach Compliance Code	compliant	compliant	compliant	compli	compli	unknow	compli	compli
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
最长访问时间	40 ns	40 ns	40 ns	40 ns	25 ns	25 ns	25 ns	25 ns
周期时间	30 ns	30 ns	30 ns	30 ns	15 ns	15 ns	15 ns	15 ns
JESD-30 代码	R-XDIP-T28	R-XDFP-F28	R-XDIP-T28	R-XDFP-F28	R-XDIP-T28	X-XUUC-N	X-XUUC-N	R-XDFP-F28
内存密度	147456 bit	147456 bit	147456 bit	147456 bi	147456 bi	147456 bi	147456 bi	147456 bi
内存宽度	9	9	9	9	9	9	9	9
功能数量	1	1	1	1	1	1	1	1
字数	16384 words	16384 words	16384 words	16384 words	16384 words	16384 words	16384 words	16384 words
字数代码	16000	16000	16000	16000	16000	16000	16000	16000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
组织	16KX9	16KX9	16KX9	16KX9	16KX9	16KX9	16KX9	16KX9
可输出	NO	NO	NO	NO	NO	NO	NO	NO
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	DIP	DFP	DIP	DFP	DIP	DIE	DIE	DFP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	UNSPECIFIED	UNSPECIFIED	RECTANGULAR
封装形式	IN-LINE	FLATPACK	IN-LINE	FLATPACK	IN-LINE	UNCASED CHIP	UNCASED CHIP	FLATPACK
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
认证状态	Qualified	Qualified	Qualified	Qualified	Qualified	Not Qualified	Not Qualified	Not Qualified
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	NO	YES	NO	YES	NO	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
端子形式	THROUGH-HOLE	FLAT	THROUGH-HOLE	FLAT	THROUGH-HOLE	NO LEAD	NO LEAD	FLAT
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	UPPER	UPPER	DUAL
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	-	不符合	不符合
厂商名称	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	-
针数	28	28	28	28	28	-	-	28
其他特性	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT	-	-	-
最大时钟频率 (fCLK)	25 MHz	25 MHz	25 MHz	25 MHz	40 MHz	-	-	-
JESD-609代码	e4	e4	e4	e4	e4	-	-	-
内存集成电路类型	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	-	-	-
端子数量	28	28	28	28	28	-	-	28
封装等效代码	DIP28,.3	FL28,.4	DIP28,.3	FL28,.4	DIP28,.3	-	-	-
电源	5 V	5 V	5 V	5 V	5 V	-	-	-
筛选级别	MIL-PRF-38535 Class V	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	-	-	-
座面最大高度	3.94 mm	3.3 mm	3.94 mm	3.3 mm	3.94 mm	-	-	3.3 mm
最大压摆率	0.11 mA	0.11 mA	0.11 mA	0.11 mA	0.12 mA	-	-	-
端子面层	Gold (Au)	Gold (Au)	Gold (Au)	Gold (Au)	Gold (Au)	-	-	-
端子节距	2.54 mm	1.27 mm	2.54 mm	1.27 mm	2.54 mm	-	-	1.27 mm
宽度	7.62 mm	10.16 mm	7.62 mm	10.16 mm	7.62 mm	-	-	10.16 mm
Base Number Matches	1	1	1	-	1	1	-	1

5962D9317707VTC

5962D9317707VTC概述

5962D9317707VTC规格参数

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5962D9317707VTC相似产品对比

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