Datasheet> 器件分类 > 存储> 存储> MMDP-672061HV-30

文档预览

MMDP-672061HV-30: 产品描述FIFO, 16KX9, 30ns, Asynchronous, CMOS, 0.400 INCH, DFP-28; 产品类别存储存储; 文件大小607KB，共20页; 制造商Atmel (Microchip)

下载文档详细参数选型对比全文预览

MMDP-672061HV-30概述

FIFO, 16KX9, 30ns, Asynchronous, CMOS, 0.400 INCH, DFP-28

MMDP-672061HV-30规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	Atmel (Microchip)
零件包装代码	DFP
包装说明	DFP, FL28,.4
针数	28
Reach Compliance Code	compli
ECCN代码	EAR99
最长访问时间	30 ns
周期时间	40 ns
JESD-30 代码	R-XDFP-F28
JESD-609代码	e0
内存密度	147456 bi
内存集成电路类型	OTHER FIFO
内存宽度	9
功能数量	1
端子数量	28
字数	16384 words
字数代码	16000
工作模式	ASYNCHRONOUS
最高工作温度	125 °C
最低工作温度	-55 °C
组织	16KX9
可输出	NO
封装主体材料	UNSPECIFIED
封装代码	DFP
封装等效代码	FL28,.4
封装形状	RECTANGULAR
封装形式	FLATPACK
并行/串行	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	5 V
认证状态	Not Qualified
座面最大高度	3.3 mm
最大待机电流	0.005 A
最大压摆率	0.11 mA
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	4.5 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	CMOS
温度等级	MILITARY
端子面层	Tin/Lead (Sn/Pb)
端子形式	FLAT
端子节距	1.27 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	10.16 mm

文档预览

下载PDF文档

全文
预览

Features

•

First-in First-out Dual Port Memory

16384 bits x 9 Organization

Fast Flag and Access Times: 15, 30 ns

Wide Temperature Range: -55°C to +125°C

Programmable Half Full Flag

Fully Expandable by Word Width or Depth

Asynchronous Read/Write Operations

Empty, Full and Half Flags in Single Device Mode

Retransmit Capability

Bi-directional Applications

Battery Back-up Operation: 2V Data Retention

TTL Compatible

Single 5V + 10% Power Supply

No Single Event Latch Up Below an LET threshold of 80 MeV/mg/cm

Tested up to a Total Dose of 30 Krads (accorcing to MIL-STD-883 TM1019)

QML Q and V with SMD 5962-93177

ESSC B with Specification 9301/48

Description

The M672061H implements a first-in first-out algorithm, featuring asynchronous

read/write operations. The FULL and EMPTY flags prevent data overflow and under-

flow. The Expansion logic allows unlimited expansion in word size and depth with no

timing penalties. Twin address pointers automatically generate internal read and write

addresses, and no external address information are required for the Atmel FIFOs.

Address pointers are automatically incremented with the write pin and read pin. The 9

bits wide data are used in data communications applications where a parity bit for

error checking is necessary. The Retransmit pin resets the Read pointer to zero with-

out affecting the write pointer. This is very useful for retransmitting data when an error

is detected in the system.

Using an array of eight transistors (8T) memory cell, the M672061H combines an

extremely low standby supply current (typ = 0.1 µA) with a fast access time at 15 ns

over the full temperature range. All versions offer battery backup data retention capa-

bility with a typical power consumption at less than 2 µW.

For military/space applications that demand superior levels of performance and reli-

ability the M672061H is processed according to the methods of the latest revision of

the MIL PRF 38535 (Q and V) or ESA SCC 9000.

Rad. Tolerant

High Speed

16 Kb x 9

Parallel FIFO with

Programmable

Flag

M672061H

4144I–AERO–05/04

Figure 2.

Reset (write (read) to Programmable Half Full Flag register)

Write Enable (W)

A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.

Data set-up and hold times must be maintained in the rise time of the leading edge of

the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any

current read operation.

Once half the memory is filled, and during the falling edge of the next write operation,

the Half-Full Flag (HF) will be set to low and remain in this state until the difference

between the write and read pointers is less than or equal to half of the total available

memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the

read operation.

To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-

tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,

allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is

blocked from W, so that external changes to W will have no effect on the full FIFO stack.

Read Enable (R)

A read cycle is initiated on the falling edge of the Read Enable (R) provided that the

Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not including

any current write operations. After Read Enable (R) goes high, the Data Outputs

(Q0 - Q8) will return to a high impedance state until the next Read operation. When all

the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the

“final” read cycle, but inhibiting further read operations while the data outputs remain in

a high impedance state. Once a valid write operation has been completed, the Empty

Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO

stack is empty, the internal read pointer is blocked from R, so that external changes to R

will have no effect on the empty FIFO stack.

This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to

ground to indicate that it is the first loaded (see Operating Modes). In the Single Device

Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-

necting the Expansion In (XI) to ground.

The M672061H can be set to retransmit data when the Retransmit Enable Control (RT)

input is pulsed low. A retransmit operation will set the internal read point to the first loca-

tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be

in the high state during retransmit. The retransmit feature is intended for use when a

number of writes are equal to or less than the depth of the FIFO has occured since the

last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode

and will affect the Half-Full Flag (HF), in accordance with the relative locations of the

read and write pointers.

First Load/Retransmit

(FL/RT)

M672061H

4144I–AERO–05/04

M672061H

Expansion In (XI)

This input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an

operation in the single device mode. Expansion In (XI) is connected to Expansion Out

(XO) of the previous device in the Depth Expansion or Daisy Chain modes.

The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is

one location less than the read pointer, indicating that the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.

The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer

is equal to the write pointer, indicating that the device is empty.

This is a dual-purpose output. In the single device mode, when Expansion In (XI) is con-

nected to ground, this output acts as an indication of a half-full memory.

The M672061H offers a variable offset for the Half Full condition. The offset is loaded

into a register during a reset cycle. When RS is low, the Programmable Half Full Flag

(PHF) can be loaded from the DATA inputs I

- I

by pulsing W low or from the DATA

outputs Q

- Q

by pulsing R low. The offset options are listed in table 1. If PHF is not

loaded during the reset cycle, the default offset will be the half of the total memory of the

device.

The Programmable Half-Full Flag (PHF) will be set to low and will remain set until the

difference between the write and read pointers is less than or equal to the Programma-

ble offset (if the Half Full Flag register has been loaded during the reset cycle) or the half

of the total memory (if the Half Full register has not been loaded during the reset cycle).

After half the memory is filled and on the falling edge of the next write operation, the

Half-Full Flag (HF) will be set to low and will remain set until the difference between the

write and read pointers is less than or equal to half of the total memory of the device.

The Half-Full Flag (HF) is then reset by the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of

the previous device. This output acts as a signal to the next device in the Daisy Chain by

providing a pulse to the next device when the previous device reaches the last memory

location.

Full Flag (FF)

Empty Flag (EF)

Expansion Out/Half-full

Flag (XO/HF)

Data Output (Q

- Q

)

DATA output for 9-bit wide data. This data is in a high impedance condition whenever

Read (R) is in a high state.

4144I–AERO–05/04

MMDP-672061HV-30相似产品对比

	MMDP-672061HV-30	SMCP-672061HV-15SB	SMDP-672061HV-15SB	MMDP-672061HV-15	SMCP-672061HV-30SB	MMCP-672061HV-15	SMDP-672061HV-30SB	MMCP-672061HV-30
描述	FIFO, 16KX9, 30ns, Asynchronous, CMOS, 0.400 INCH, DFP-28	FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	FIFO, 16KX9, 15ns, Asynchronous, CMOS, 0.400 INCH, DFP-28	FIFO, 16KX9, 15ns, Asynchronous, CMOS, 0.400 INCH, DFP-28	FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	FIFO, 16KX9, 30ns, Asynchronous, CMOS, 0.400 INCH, DFP-28	FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28
是否无铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
零件包装代码	DFP	DIP	DFP	DFP	DIP	DIP	DFP	DIP
包装说明	DFP, FL28,.4	DIP, DIP28,.3	DFP, FL28,.4	DFP, FL28,.4	DIP, DIP28,.3	DIP, DIP28,.3	DFP, FL28,.4	DIP, DIP28,.3
针数	28	28	28	28	28	28	28	28
Reach Compliance Code	compli	compliant	compliant	compliant	compliant	compli	compli	compli
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
最长访问时间	30 ns	15 ns	15 ns	15 ns	30 ns	15 ns	30 ns	30 ns
周期时间	40 ns	25 ns	25 ns	25 ns	40 ns	25 ns	40 ns	40 ns
JESD-30 代码	R-XDFP-F28	R-CDIP-T28	R-XDFP-F28	R-XDFP-F28	R-CDIP-T28	R-CDIP-T28	R-XDFP-F28	R-CDIP-T28
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0
内存密度	147456 bi	147456 bit	147456 bit	147456 bit	147456 bit	147456 bi	147456 bi	147456 bi
内存集成电路类型	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO
内存宽度	9	9	9	9	9	9	9	9
功能数量	1	1	1	1	1	1	1	1
端子数量	28	28	28	28	28	28	28	28
字数	16384 words	16384 words	16384 words	16384 words	16384 words	16384 words	16384 words	16384 words
字数代码	16000	16000	16000	16000	16000	16000	16000	16000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
组织	16KX9	16KX9	16KX9	16KX9	16KX9	16KX9	16KX9	16KX9
可输出	NO	NO	NO	NO	NO	NO	NO	NO
封装主体材料	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED	UNSPECIFIED	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED
封装代码	DFP	DIP	DFP	DFP	DIP	DIP	DFP	DIP
封装等效代码	FL28,.4	DIP28,.3	FL28,.4	FL28,.4	DIP28,.3	DIP28,.3	FL28,.4	DIP28,.3
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	FLATPACK	IN-LINE	FLATPACK	FLATPACK	IN-LINE	IN-LINE	FLATPACK	IN-LINE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	3.3 mm	3.94 mm	3.3 mm	3.3 mm	3.94 mm	3.94 mm	3.3 mm	3.94 mm
最大待机电流	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A
最大压摆率	0.11 mA	0.12 mA	0.12 mA	0.12 mA	0.11 mA	0.12 mA	0.11 mA	0.11 mA
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	NO	YES	YES	NO	NO	YES	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	FLAT	THROUGH-HOLE	FLAT	FLAT	THROUGH-HOLE	THROUGH-HOLE	FLAT	THROUGH-HOLE
端子节距	1.27 mm	2.54 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	1.27 mm	2.54 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	10.16 mm	7.62 mm	10.16 mm	10.16 mm	7.62 mm	7.62 mm	10.16 mm	7.62 mm
厂商名称	Atmel (Microchip)	-	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)

推荐资源

吴汉明：未来半导体产能缺口或相当于8个中芯国际: 通信世界网消息（CWW）中国半导体行业在过去一年间饱经风霜与挑战，但在业绩上仍旧保持增长。面对前方的重重阻碍，加快自主可控的步伐是众心所向。中国工程院院士、浙江大学微纳电子学院院长吴 ......; okhxyyo 单片机

Space X“重型猎鹰”运载火箭首飞成功，将特斯拉跑车送上天，马斯克再次改写历史！: 昨天，Space X“重型猎鹰”运载火箭首飞成功，将特斯拉跑车送上天，埃隆马斯克再次改写历史！为此EEWORLD大学堂特地为大家整理了几个视频，便于你们更深入的了解此事 https://training.ee ......; EE大学堂大学堂专版

有人用过S25FL512S这款flash没: 最近在调试spansion的FL512S这款flash芯片，发现芯片无法擦除，无论任何地址，读取的数据都是最后一次写入操作的数据。希望有用过这款芯片的大能告诉我怎么回事。 ...; 530lsj ARM技术

请问各位高手，北桥芯片具体什么作用啊？: 我有个疑问，就是主板上的北桥芯片起什么作用，虽然在网上一搜一大堆，但无非就是说是连接CPU和内存，AGP,的作用，起中间枢纽的作用，回答的非常初级，也没有作实质上的解释，但我想知道的是， ......; moto_jfx 嵌入式系统

运动控制器的芯片选型: 最近在筹备运动控制器，要求至少3轴联动，定位精度0.01mm，伺服周期1ms以下，可实现空间圆弧插补。看了TI公司的F2810、F2812、F28235、F28335、F28345，低价格的F28035、F2802；F28335和F2834 ......; 与非门嵌入式系统

出BBB4.3寸 BBB LCD模块 DIY LCD4 显示屏: 本帖最后由 wytalfred 于 2014-7-26 16:01 编辑参数特性：LCD：4.3寸LCD显示屏。分辨率：480x272触摸输入：电阻屏使用方式：用USB连接电脑，或者用5v电源供电，或者用电池cape（我正在设计 ......; wytalfred 淘e淘

手机无线芯片出货量放缓但前景可期

　　市场研究集团Forward Concepts通过对WSTS的最新半导体出货量统计数据进行分析，认为尽管出现了手机芯片的出货量放缓现象，但对统计的数据表示质疑。　　手机专用DSP和RISC芯片的五月份出货量比四月份增加了8%，从去年五月份累计增长率为47%。　　Forward Concepts的总裁Will Strauss同时也指出，WSTS的报告称用于无线设备的DSP五月份出货量比四...[详细]
基于FPGA的核物理实验定标器的设计实现

　　定标器在大学实验中有很广泛的应用，其中近代物理实验中的核物理实验里就有2个实验（G-M计数管和β吸收）要用到高压电源和定标器，而目前现有的设备一般使用的是分立元器件，已严重老化，高压极不稳定，维护也较为困难；另一方面在许多常用功能上明显欠缺，使得学生的实验课难以维持。为此我们提出了一种新的设计方案：采用EDA进行结构设计，充分发挥FPGA（Field Programmable Gate Ar...[详细]
医疗器械产品的人机界面设计与控制

　　虽然不当的医械产品设计并不总是和医械产品相关失误联系在一起的。对用户的研究表明，缺乏足够的培训占此类失误原因的70％到90％。但是即便这些责任人可能已经被“责罚”了，还是存在其它对病人造成危害的因素，其中之一就是不当的人机界面设计很多失曝都是隐藏在常规的医疗工作和医械产品使用之中，给不知情的医生和病人带来灾难。医疗器械与用户有直接关系的就是医疗器械的人机界面。人机界面设汁的优劣关系到医...[详细]
英特尔下周一将发布迅驰2平台

　　随着笔记本电脑出货量开始超过台式电脑的出货量，每一次推出新的笔记本电脑平台对于英特尔来说都是非常重要的。英特尔将在7月14日星期一推出迅驰2平台，这个产品原来的代号是“Montevina”。由于英特尔自己为这个平台制作的集成的图形卡出现了问题，迅驰2平台的推出比英特尔原来的计划晚了几个星期。　　事实上，采用英特尔自己的集成的图形卡的迅驰2笔记本电脑在下周一还不能上市。下周一上市的只有配置...[详细]
最新技术为ADC器件发展注入强劲动力

　　10多年来，模数转换器(ADC)作为产业发展助力剂已在工业过程控制、医疗仪器、通信系统和雷达等产品中得到广泛应用。其参数性能的不断提高使得这些‘蓝领’器件能紧跟上最新技术要求。　　2007年2月份在旧金山举办的国际固态电路会议(ISSCC)展示了ADC的丰收成果。有关Nyquist Track的大量论文重新定义了这方面的技术发展水平，其中有两个已进入新的领域。另外也不要忘记来自一般怀疑者...[详细]
数字助听器的设计挑战

　　助听器的设计人员有着严格的技术要求。助听器必须足够小以便放入人体的耳内或耳后，运行功率必须超低，并且没有噪声或失真。为满足这些要求，现有的助听设备消耗的功率要低于 1mA，工作电压为 1V，利用的芯片面积少于 10mm2，这通常意味着两个或三个设备相互叠放。典型的模拟助听器由具有非线性输入/输出功能和频率相关增益的放大器组成。但此模拟处理依赖于自定义电路，与数字处理相比，缺乏可编程性且成本更高...[详细]
PSoC电容式触摸感应技术

　　PSoC是由Cypress半导体公司推出的具有数字和模拟混合处理能力的可编程片上系统芯片，某些系列的PSoC（如CY8C21X34系列），由于其内部配备的特殊资源，使得它可以很容易地实现电容式触摸感应功能，仅需少量的几个外置分立元件，可以将每一个通用的I/O都配置为电容感应输入。　　电容式触摸感应原理如图1所示，电路板上两块相邻的覆铜之间存在一个固有的寄生电容Cp，当手指（或其他导体）靠近时...[详细]
热量带来的棘手问题

　　在大多数情况下保持心脏环境的紧凑和温暖是有益的，但是对于电子心脏扫描仪却是另一回事了。当GE医疗在设计一种据称是目前最快成像速度的扫描仪时，高速运行的芯片需要大功率能量供给，结果导致温度升高而影响系统运行的稳定性。　　工程师们几乎没有想到用硅酮胶帮助散热，能成为这个设计方案获得成功的关键因素。当他们开始寻找散热方法时，GE SilCool LTR silicone提供了一种散热解决方案。...[详细]
磁共振成像(MRI)

　　医疗成像正在取得显著进步。磁共振成像有助于检查患者体内的组织活动，可提供优质的软组织对比图像。ST提供从分立器件到32位数字处理器和存储器的广泛产品组合，帮助进一步加强磁共振成像应用。以下结构方块图可帮助您在众多推荐的适用产品中进行选择。 ...[详细]
计算机断层扫描(CT)

　　医疗成像领域正在发生日新月异的变化。计算机断层扫描可帮助患者进行成像检查。ST 提供从分立器件到32位数字处理器及存储器的广泛产品组合，可进一步加强计算机断层扫描应用。以下结构方块图可帮助您在众多推荐的适用产品中进行选择。 ...[详细]
血液分析仪

　　普通的血液分析仪具有的功能包括：平板显示、数据记录和主机通信。以下结构方块图可帮助您在众多推荐的适用产品中进行选择。 ...[详细]
FOX ELECTRONICS 推出新的低成本振荡器

2008 年7月,Fox Electronics 推出了一种抖动极低的小型硅振荡器。该振荡器的 LVDS 和 LVPECL 版本属于 Fox 新的 XpressO(tm) 系列，成本比传统的 LVDS/LVPECL 石英晶体振荡器要低30%。减噪 DSM 技术和专有的低噪音架构使这一3.3伏的 XpressO 振荡器能够减低抖动和相位噪音。其革命性的设计和专用集成电路 (...[详细]
美国晶像推出全新InstaPort加快HDMI切换

2008 年 7 月 15 日美国晶像宣布推出全新的 InstaPort™ 技术，旨在提高 HDMI 数字电视 (DTV) 的智能性，进而缩短切换滞后时间。与此同时，该公司还推出了 Silicon Image SiI9285 、 SiI9287 、 SiI9251 与 SiI9261 等一系列配套使用的端口处理器，以及全...[详细]
看高清必读数字电视有哪些优势及功能

　　随着中央电视台这月6套数字电视的开播，和中国数字电视国家标准的最后正式确定，人们期望能看到如电影般清晰的电视节目将成为现实。如今提到数字电视这个词，也许您并不陌生，大家对数字电视已经耳熟能详。但实际上，说到什么是数字电视？它到底能给我们带来什么？怎样才能看上数字电视……可能多数人还是会一头雾水。本次我们就从数字电视的基本知识入手，希望通过对本文的了解让您了解数字电视的魅力。　　一、什么是数...[详细]
数字信号处理（DSP ）系统测试和调试3

　　仿真的基本原理　　仿真是一种被用在嵌入式系统开发领域的技术。它可以给系统开发者带来集成硬件和软件所需的可控制性和可视性，有效地模仿DSP 处理器的电气特征和性能，同时让工程师更清晰地了解处理器的活动并加以控制。　　仿真器包含了硬件和软件技术。仿真硬件方面由DSP 芯片上的功能构成，它可以采集数据。该数据提供了有关系统活动状态和其它可视性的信息。硬件还需要从DSP 设备上高速获取此类信息，...[详细]

器件捷径: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多

随便看看