MD18R3268(G)AG0
Change History
Version 0.1 (Sept. 2003)-
Preliminary
* First copy.
* Based on version 1.0 (July 2002) 256/288Mbit D-die 32 Bit RIMM
Module Datasheet
Version 1.0 (Feb. 2004)
* Eliminate “Preliminary”
Version 1.0 Feb. 2004
MD18R3268(G)AG0
(32Mx18)*8(16)pcs 32 Bit RIMM
Module based on 576Mb A-die, 32s banks,32K/32ms Ref, 2.5V
Overview
The 32 Bit RIMM
®
module is a general purpose high-perfor-
mance line of memory modules suitable for use in a broad
range of applications including computer memory, personal
computers, workstations, and other applications where high
bandwidth and low latency are required.
The 32 Bit RIMM module consists of 576Mb RDRAM
®
devices. These are extremely high-speed CMOS DRAMs
organized as 32M words by 18 bits. The use of Rambus
Signaling Level (RSL) technology permits the use of
conventional system and board design technologies. The 32
Bit RIMM module supports transfer rate per pin from 800 to
1200MHz, resulting in repective total module bandwidth
from 3200MB/s or 3.2GB/s for RIMM 3200 modules to
4800MB/s or 4.8GB/s for RIMM 4800 modules.
The 32 Bit RIMM module provides two independent 18 bit
memory channels to facilitate compact system design. The
"Thru" Channel enters and exits the module to support a
connection to or from a controller, memory slot, or termina-
tion. The "Term" Channel is terminated on the module and
supports a connection from a controller or another memory
slot.
The RDRAM architecture enables the highest sustained
bandwidth for multiple, simultaneous, randomly addressed
memory transactions. The separate control and data buses
with independent row and column control yield over 95%
bus efficiency. The RDRAM device multi-bank architecture
supports up to four simultaneous transactions per device.
Key Timing Parameters
The following table lists the frequency and latency bins
available for 32 Bit RIMM modules.
Table 1: 32 Bit RIMM Module Frequency and Latency
Speed
RAC
Organi-
(Row
zation I/O Freq.
Access
(MHz)
Time)
t
Part Number
ns
128Mx36
RIMM 4800
256Mx36
128Mx36
RIMM 4200
256Mx36
128Mx36
RIMM 3200
256Mx36
800MHz
40
MD18R326GAG0-CM8
1066MHz
32P
MD18R326GAG0-CT9
MD18R3268AG0-CM8
1200MHz
32
MD18R326GAG0-CN1
MD18R3268AG0-CT9
MD18R3268AG0-CN1
Form Factor
The 32 Bit RIMM modules are offered in 232-pad 1mm edge
connector pad pitch suitable for 232 contact RIMM connec-
tors. Figure 1 below, shows a sixteen device 32 Bit RIMM
module.
Features
♦
2 Independent RDRAM channels, 1 pass through and 1
♦
High speed 800, 1066 and 1200MHz RDRAM devices
♦
232 edge connector pads with 1mm pad spacing
♦
Module PCB size: 133.35mm x 34.93mm x 1.27mm
♦
Each RDRAM device has 32 banks, for a total of 512, 256 banks
on each 1152MB, 576MB module respectively
(5.25” x 1.375” x 0.05”)
terminated on 32 Bit RIMM module
♦
Gold plated edge connector pad contacts
♦
Serial Presence Detect (SPD) support
♦
Operates from a 2.5 volt supply (±5%)
♦
Low power and powerdown self refresh modes
♦
Separate Row and Column buses for higher efficiency
♦
WBGA lead free package (92 balls)
Note: On double sided modules, RDRAM devices are also installed on bottom side of PCB.
Figure 1 : 32 Bit RIMM module with heat spreader removed
Page 1
Version 1.0 Feb. 2004
MD18R3268(G)AG0
Table 2: Module Pad Numbers and Signal Names
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
Pin Name
Gnd
SCK_THRU_L
Gnd
DQA8_THRU_L
Gnd
DQA6_THRU_L
Gnd
DQA4_THRU_L
Gnd
DQA2_THRU_L
Gnd
DQA0_THRU_L
Gnd
CFM_THRU_L
Gnd
CFMN_THRU_L
Gnd
ROW1_THRU_L
Gnd
COL4_THRU_L
Gnd
COL2_THRU_L
Gnd
COL0_THRU_L
Gnd
DQB1_THRU_L
Gnd
DQB3_THRU_L
Gnd
DQB5_THRU_L
Gnd
DQB7_THRU_L
Gnd
SOUT_THRU
Gnd
DQB8_THRU_R
Gnd
DQB6_THRU_R
Gnd
DQB4_THRU_R
Gnd
DQB2_THRU_R
Gnd
DQB0_THRU_R
Gnd
COL1_THRU_R
Pin
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
Pin Name
Gnd
CMD_THRU_L
Gnd
DQA7_THRU_L
Gnd
DQA5_THRU_L
Gnd
DQA3_THRU_L
Gnd
DQA1_THRU_L
Gnd
CTMN_THRU_L
Gnd
CTM_THRU_L
Gnd
ROW2_THRU_L
Gnd
ROW0_THRU_L
Gnd
COL3_THRU_L
Gnd
COL1_THRU_L
Gnd
DQB0_THRU_L
Gnd
DQB2_THRU_L
Gnd
DQB4_THRU_L
Gnd
DQB6_THRU_L
Gnd
DQB8_THRU_L
Gnd
SIN_THRU
Gnd
DQB7_THRU_R
Gnd
DQB5_THRU_R
Gnd
DQB3_THRU_R
Gnd
DQB1_THRU_R
Gnd
COL0_THRU_R
Gnd
COL2_THRU_R
Pin
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
Pin Name
Gnd
Vterm
Vterm
Gnd
DQA3_THRU_R
Gnd
DQA5_THRU_R
Gnd
DQA7_THRU_R
Gnd
Vdd
Gnd
SCK_THRU_R
Gnd
CMD_THRU_R
Gnd
Vref
Vdd
SVdd
Vdd
SCL
Vdd
SA0
Vdd
SA2
Gnd
DQB8_TERM
Gnd
DQB6_TERM
Gnd
DQB4_TERM
Gnd
DQB2_TERM
Gnd
DQB0_TERM
Gnd
COL1_TERM
Gnd
COL3_TERM
Gnd
ROW0_TERM
Gnd
ROW2_TERM
Gnd
CTM_TERM_R
Gnd
Pin
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B95
B96
B97
B98
B99
B100
B101
B102
B103
B104
Pin Name
Gnd
Vterm
Vterm
Gnd
DQA4_THRU_R
Gnd
DQA6_THRU_R
Gnd
DQA8_THRU_R
Gnd
Vdd
Gnd
CTMN_TERM_L
Gnd
CTM_TERM_L
Gnd
Vcmos
Vdd
SWP
Vdd
SDA
Vdd
SA1
Vdd
SIN_TERM
Gnd
DQB7_TERM
Gnd
DQB5_TERM
Gnd
DQB3_TERM
Gnd
DQB1_TERM
Gnd
COL0_TERM
Gnd
COL2_TERM
Gnd
COL4_TERM
Gnd
ROW1_TERM
Gnd
CFMN_TERM
Gnd
CFM_TERM
Gnd
Page 2
Version 1.0 Feb. 2004
MD18R3268(G)AG0
Table 2: Module Pad Numbers and Signal Names (Continued)
Pin
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
Pin Name
Gnd
COL3_THRU_R
Gnd
ROW0_THRU_R
Gnd
ROW2_THRU_R
Gnd
CTM_THRU_R
Gnd
CTMN_THRU_R
Gnd
DQA1_THRU_R
Pin
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
Pin Name
Gnd
COL4_THRU_R
Gnd
ROW1_THRU_R
Gnd
CFMN_THRU_R
Gnd
CFM_THRU_R
Gnd
DQA0_THRU_R
Gnd
DQA2_THRU_R
Pin
A105
A106
A107
A108
A109
A110
A111
A112
A113
A114
A115
A116
Pin Name
CTMN_TERM_R
Gnd
DQA1_TERM
Gnd
DQA3_TERM
Gnd
DQA5_TERM
Gnd
DQA7_TERM
Gnd
CMD_TERM
Gnd
Pin
B105
B106
B107
B108
B109
B110
B111
B112
B113
B114
B115
B116
Pin Name
DQA0_TERM
Gnd
DQA2_TERM
Gnd
DQA4_TERM
Gnd
DQA6_TERM
Gnd
DQA8_TERM
Gnd
SCK_TERM
Gnd
Table 3: Module Connector Pad Description
Signal
Module Connector Pads
I/O
Type
Description
Clock From Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for receiving RSL signals from the
controller. Positive polarity.
Clock From Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for receiving RSL signals from the
controller. Positive polarity.
Clock From Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for receiving RSL signals from the
controller. Negative polarity.
Clock From Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for receiving RSL signals from the
controller. Negative polarity.
CFM_THRU_L
A14
I
RSL
CFM_THRU_R
B54
I
RSL
CFMN_THRU_L
A16
I
RSL
CFMN_THRU_R
B52
I
RSL
CMD_THRU_L
B2
I
Serial Command Input used to read from and write to the control
V
CMOS
registers. Also used for power management. Connects to left
RDRAM device on "Thru" Channel.
Serial Command Input used to read from and write to the control
V
CMOS
registers. Also used for power management. Connects to right
RDRAM device on "Thru" Channel.
RSL
"Thru" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to left RDRAM
device on "Thru" Channel.
"Thru" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to right
RDRAM device on "Thru" Channel.
Clock To Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to the
controller. Positive polarity.
CMD_THRU_R
A73
I
COL4_THRU_L..C
OL0_THRU_L
COL4_THRU_R..C
OL0_THRU_R
A20, B20, A22, B22, A24
I
B48, A48, B46, A46, B44
I
RSL
CTM_THRU_L
B14
I
RSL
Page 3
Version 1.0 Feb. 2004
MD18R3268(G)AG0
Table 3: Module Connector Pad Description (Continued)
Signal
Module Connector Pads
I/O
Type
Description
Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to the
controller. Positive polarity.
Clock To Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to the
controller. Negative polarity.
Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to the
controller. Negative polarity.
"Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to left RDRAM device on "Thru" Channel.
DQA8_THRU_L is non-functional on modules with x16 RDRAM
devices.
"Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to right RDRAM device on "Thru" Channel.
DQA8_THRU_R is non-functional on modules with x16 RDRAM
devices.
"Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to left RDRAM device on "Thru" Channel.
DQB8_THRU_L is non-functional on modules with x16 RDRAM
devices.
"Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to right RDRAM device on "Thru" Channel.
DQB8_THRU_R is non-functional on modules with x16 RDRAM
devices.
Row bus. 3-bit bus containing control and address information for
row accesses. Connects to left RDRAM device on "Thru" Channel.
Row bus. 3-bit bus containing control and address information for
row accesses. Connects to right RDRAM device on "Thru" Chan-
nel.
CTM_THRU_R
A54
I
RSL
CTMN_THRU_L
B12
I
RSL
CTMN_THRU_R
A56
I
RSL
DQA8_THRU_L..
DQA0_THRU_L
A4, B4, A6, B6, A8, B8,
A10, B10, A12
I/O
RSL
DQA8_THRU_R..
DQA0_THRU_R
B67, A67, B65, A65, B63,
A63, B58, A58, B56
I/O
RSL
DQB8_THRU_L..
DQB0_THRU_L
B32, A32, B30, A30, B28,
A28, B26, A26, B24
I/O
RSL
DQB8_THRU_R..
DQB0_THRU_R
A36, B36, A38, B38, A40,
B40, A42, B42, A44
I/O
RSL
ROW2_THRU_L..
ROW0_THRU_L
ROW2_THRU_R..
ROW0_THRU_R
B16, A18, B18
I
RSL
A52, B50, A50
I
RSL
SCK_THRU_L
A2
I
Serial Clock input. Clock source used to read from and write to
V
CMOS
"Thru" Channel RDRAM control registers. Connects to left
RDRAM device on "Thru" Channel.
Serial Clock input. Clock source used to read from and write to
V
CMOS
"Thru" Channel RDRAM control registers. Connects to right
RDRAM device on "Thru" Channel.
"Thru" Channel Serial I/O for reading from and writing to the con-
V
CMOS
trol registers. Attaches to SIO0 of right RDRAM device on "Thru"
Channel.
SCK_THRU_R
A71
I
SIN_THRU
B34
I/O
Page 4
Version 1.0 Feb. 2004