THC63LVD823_Rev2.0
THC63LVD823
Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA
General Description
The THC63LVD823 transmitter is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA+ resolutions and Dual Link trans-
mission between Host and Flat Panel Display up to
UXGA resolutions.
The THC63LVD823 converts 48bits of CMOS/TTL
data into LVDS(Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for ris-
ing edge or falling edge clocks through a dedicated pin.
In Single Link, the transmit clock frequency of
135MHz, 48bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 472Mbytes per
second.
In Dual Link, the transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
Features
•
Wide dot clock range: 25-135MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
•
PLL requires No external components
•
Supports Dual Link, Dual-in (TTL)/Dual-out
(LVDS) pixel up to 170MHz dot clock for UXGA
•
Supports Single Link, Dual-in (TTL)/Single-out
•
•
•
•
•
•
•
(LVDS) pixel up to 135MHz dot clock for SXGA+
Supports Single Link, Single-in (TTL)/Single-out
(LVDS) pixel up to 85MHz dot clock for XGA
Clock edge selectable
Supports Reduced swing LVDS for Low EMI
Power down mode
Low power single 3.3V CMOS design
100pin TQFP
THC63LVDM83R compatible
Block Diagram
CMOS/TTL INPUT
8
MUX
8
8
8
8
8
PARALLEL TO SERIAL
LVDS OUTPUT
RED1
1st DATA
GREEN1
BLUE1
TA1 +/-
TB1 +/-
TC1 +/-
TD1 +/-
TCLK1 +/-
(25 to 135MHz)
1st Link
HSYNC
VSYNC
DE
TA2 +/-
PARALLEL TO SERIAL
8
8
8
TB2 +/-
TC2 +/-
TD2 +/-
TCLK2 +/-
(25 to 85MHz)
2nd Link
RED2
2nd DATA
GREEN2
BLUE2
TRANSMITTER CLOCK IN
(25 to 85MHz)
R/F
/PDWN
PLL
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
1
THine Electronics, Inc.
THC63LVD823 _Rev2.0
Pin Out
75
B15
B16
B17
R20
R21
R22
R23
R24
R25
R26
R27
VCC
GND
G20
G21
G22
G23
G24
G25
G26
G27
B20
B21
B22
B23
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
B13
B12
GND
VCC
B11
B10
G17
G16
G15
G14
G13
G12
G11
G10
R17
R16
R15
R14
GND
VCC
R13
R12
R11
R10
B14
LVDS GND
TA1-
TA1+
TB1-
TB1+
LVDS VCC
TC1-
TC1+
TCLK1-
TCLK1+
TD1-
TD1+
LVDS GND
TA2-
TA2+
TB2-
TB2+
LVDS VCC
TC2-
TC2+
TCLK2-
TCLK2+
TD2-
TD2+
LVDS GND
1
B24
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
B25
VCC
GND
B26
B27
HSYNC
VSYNC
DE
CLKIN
R/F
RS
TEST1
TEST2
MODE1
MODE0
OE
6/8
/PDWN
TEST3
TEST4
TEST5
PLL GND
PLL VCC
PLL GND
2
THine Electronics, Inc.
THC63LVD823 _Rev2.0
Pin Description
Pin Name
TA1+, TA1-
TB1+, TB1-
TC1+, TC1-
TD1+, TD1-
TCLK1+, TCLK1-
TA2+, TA2-
TB2+, TB2-
TC2+, TC2-
TD2+, TD2-
TCLK2+, TCLK2-
R17 ~ R10
G17 ~ G10
B17 ~ B10
R27 ~ R20
G27 ~ G20
B27 ~ B20
DE
VSYNC
HSYNC
CLKIN
TEST1, TEST5
TEST3, TEST4
TEST2
/PDWN
6/8
OE
Pin #
48, 49
46, 47
43, 44
39, 40
41, 42
36, 37
34, 35
31, 32
27, 28
29, 30
60, 59, 58, 57,
54, 53, 52, 51
68, 67, 66, 65,
64, 63, 62, 61
78, 77, 76, 75,
74, 73, 70, 69
86, 85, 84, 83,
82, 81, 80, 79
96, 95, 94, 93,
92, 91, 90, 89
6, 5, 2, 1, 100,
99, 98, 97
9
8
7
10
13, 22
20, 21
14
19
18
17
Type
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
Data Enable Input.
Vsync Input.
Hsync Input.
Clock Input.
Test Pins.
Test Pins, must be L for normal operation.
Test Pins, must be H for normal operation.
H: Normal operation,
L: Power down (all outputs are Hi-Z)
6bit/8bit color select.
H: 6bit (TDx+/- are GND), L: 8bit.
Output enable.
H: Output enable, L: Output disable (all outputs are Hi-Z)
Pixel Data Mode.
MODE1, MODE0
15, 16
IN
MODE1
L
L
H
MODE0
L
H
H
Mode
Dual Link (Dual-in/Dual-out)
Single Link (Dual-in/Single-out)
Single Link (Single-in/Single-out)
Description
The 1st Link. The 1st pixel output data when Dual Link.
LVDS Clock Out for 1st Link.
The 2nd Link. These pins are disabled when Single Link.
LVDS Clock Out for 2nd Link.
The 1st Pixel Data Inputs.
The 2nd Pixel Data Inputs.
RS
12
IN
LVDS swing range select.
H: Normal range, L: Reduced range.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
Pin Name
R/F
VCC
GND
LVDS VCC
LVDS GND
PLL VCC
PLL GND
Pin #
11
3, 55, 71, 87
4, 56, 72, 88
33, 45
26, 38, 50
24
23, 25
Type
IN
Power
Ground
Power
Ground
Power
Ground
Description
Input Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
Power Supply Pins for TTL inputs, output and digital
circuitry.
Ground Pins for TTL inputs, outputs and digital circuitry.
Power Supply Pins for LVDS Outputs.
Ground Pins for LVDS Outputs.
Power Supply for PLL circuitry.
Ground Pin for PLL circuitry.
Absolute Maximum Ratings
1
Supply Voltage (V
CC
)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Driver Output Voltage
Output Current
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 4sec)
Maximum Power Dissipation @+25
°C
-0.3V ~ +4.0V
-0.3V ~ (V
CC
+ 0.3V)
-0.3V ~ (V
CC
+ 0.3V)
-0.3V ~ (V
CC
+ 0.3V)
-30mA ~ 30mA
+125
°C
-55
°C
~ +125
°C
+260
°C
1.0W
Electrical Characteristics
CMOS/TTL DC Specifications
V
CC
= 3.0V ~ 3.6V, Ta = -10
°C
~ +70
°C
Symbol
V
IH
V
IL
I
INC
Parameter
High Level Input Voltage
Low Level Input Voltage
Input Current
0V
≤
V
IN
≤
V
CC
Conditions
Min.
2.0
GND
Typ.
Max.
V
CC
0.8
±
10
Units
V
V
µA
1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They
are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics”
specify conditions for device operation.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
4
THine Electronics, Inc.
THC63LVD823 _Rev2.0
LVDS Transmitter DC Specifications
V
CC
= 3.0V ~ 3.6V, Ta = -10
°C
~ +70
°C
Symbol
Parameter
Conditions
Normal
swing
Reduced
swing
Min.
250
100
Typ.
350
200
Max.
450
300
35
RL=100Ω
1.125
1.25
1.375
35
VOUT=0V, RL=100Ω
/PDWN=0V, VOUT=0V to
VCC
-24
±
10
Units
mV
mV
mV
V
mV
mA
µA
VOD
Differential Output Voltage
RL=100Ω
∆VOD
VOC
∆VOC
I
OS
I
OZ
Change in VOD between
complementary output states
Common Mode Voltage
Change in VOC between
complementary output states
Output Short Circuit Current
Output TRI-State current
Supply Current
V
CC
= 3.0V ~ 3.6V, Ta = -10
°C
~ +70
°C
Symbol
Parameter
Condition(*)
VESA SXGA ( 60Hz )
Transmitter Supply
I
TCCG
Current
(256 Gray Scale Pattern)
VESA UXGA ( 60Hz )
CLKIN=81MHz
VESA SXGA ( 60Hz )
Transmitter Supply
I
TCCW
Current
(Double Checker Pattern)
VESA UXGA ( 60Hz )
CLKIN=81MHz
I
TCCS
Transmitter Power Down
Supply Current
/PDWN = L
CLKIN=54MHz
CLKIN=54MHz
MODE<1:0>=LH
RL=100
Ω
,CL=5pF
VCC=3.3V
MODE<1:0>=LL
RL=100
Ω
,CL=5pF
VCC=3.3V
MODE<1:0>=LH
RL=100
Ω
,CL=5pF
VCC=3.3V
MODE<1:0>=LL
RL=100
Ω
,CL=5pF
VCC=3.3
10
µA
86
99
mA
53
61
mA
78
89
mA
50
58
mA
Typ.
Max.
Units
(*) VESA is a trademark of the Video Electronics Standards Association.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
5
THine Electronics, Inc.
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