THC63LVD824 _Rev2.0
THC63LVD824
Single(135MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA
General Description
The THC63LVD824 receiver is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA+ resolutions and Dual Link trans-
mission between Host and Flat Panel Display up to
UXGA resolutions. The THC63LVD824 converts the
LVDS data streams back into 48bits of CMOS/TTL data
with falling edge or rising edge clock for convenient
with a variety of LCD panel controllers.
In Single Link, data transmit clock frequency of
135MHz, 48bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 472Mbytes per
second.
In Dual Link, data transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
Features
•
Wide dot clock range: 25-170MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
•
PLL requires No external components
•
Supports Single Link up to 135MHz dot clock for
SXGA+
•
Supports Dual Link up to 170MHz dot clock for
•
•
•
•
•
•
•
UXGA
50% output clock duty cycle
TTL clock edge programmable
TTL output driverbility selectable for lower EMI
Power down mode
Low power single 3.3V CMOS design
100pin TQFP
THC63LVDF84B compatible
Block Diagram
LVDS INPUT
SERIAL TO PARALLEL
RA1 +/-
RB1 +/-
1st Link
RC1 +/-
RD1 +/-
RCLK1 +/-
(25 to 135MHz)
8
8
28
8
CMOS/TTL OUTPUT
RED1
GREEN1
BLUE1
1st DATA
HSYNC
VSYNC
DEMUX
PLL
DE
SERIAL TO PARALLEL
RA2 +/-
RB2 +/-
2nd Link
RC2 +/-
RD2 +/-
RCLK2 +/-
(25 to 85MHz)
RECEIVER CLOCK OUT
(25 to 85MHz)
8
RED2
GREEN2
BLUE2
2nd DATA
28
8
8
PLL
R/F
/PDWN
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
1
THine Electronics, Inc.
THC63LVD824 _Rev2.0
Pin Out
75
LVDS GND
RA1-
RA1+
RB1-
RB1+
LVDS VCC
RC1-
RC1+
RCLK1-
RCLK1+
RD1-
RD1+
LVDS GND
RA2-
RA2+
RB2-
RB2+
LVDS VCC
RC2-
RC2+
RCLK2-
RCLK2+
RD2-
RD2+
LVDS GND
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSYNC
HSYNC
B17
B16
GND
VCC
B15
B14
B13
B12
B11
B10
G17
G16
G15
G14
G13
GND
VCC
G12
G11
G10
R17
R16
DE
R15
GND
VCC
R14
R13
R12
R11
R10
GND
VCC
CLKOUT
B27
B26
B25
B24
B23
GND
VCC
B22
B21
B20
G27
GND
VCC
G26
1
PLL GND
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
PLL VCC
GND
/PDWN
MODE0
MODE1
GND
R/F
DRVSEL
R20
R21
R22
R23
R24
VCC
GND
R25
R26
R27
G20
G21
G22
G23
G24
G25
2
THine Electronics, Inc.
THC63LVD824 _Rev2.0
Pin Description
Pin Name
RA1+, RA1-
RB1+, RB1-
RC1+, RC1-
RD1+, RD1-
RCLK1+, RCLK1-
RA2+, RA2-
RB2+, RB2-
RC2+, RC2-
RD2+, RD2-
RCLK2+, RCLK2-
R17 ~ R10
G17 ~ G10
B17 ~ B10
R27 ~ R20
G27 ~ G20
B27 ~ B20
DE
VSYNC
HSYNC
CLKOUT
DRVSEL
R/F
Pin #
78, 77
80, 79
83, 82
87, 86
85, 84
90, 89
92, 91
95, 94
99, 98
97, 96
52, 51, 50, 47,
46, 45, 44, 43
62, 61, 60, 59,
58, 55, 54, 53
72, 71, 68, 67,
66, 65, 64, 63
19, 18, 17, 14,
13, 12, 11, 10
29, 26, 25, 24,
23, 22, 21, 20
39, 38, 37, 36,
35, 32, 31, 30
75
74
73
40
9
8
Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
Data Enable Output.
Vsync Output.
Hsync Output.
Clock Output.
Output Driverbility Select.
H: High power, L: Low power.
Output Clock Triggering Edge Select.
H: Rising edge, L: Falling edge.
Pixel Data Mode.
MODE1, MODE0
6, 5
IN
MODE1
L
L
MODE0
L
H
Mode
Dual Link
Single Link
Description
The 1st Link. The 1st pixel input data when Dual Link.
LVDS Clock Input for 1st Link.
The 2nd Link. These pins are disabled when Single Link.
LVDS Clock Input for 2nd Link.
The 1st Pixel Data Outputs.
The 2nd Pixel Data Outputs.
/PDWN
VCC
GND
LVDS VCC
LVDS GND
4
15, 27, 33, 41,
48, 56, 69
3, 7, 16, 28, 34,
42, 49, 57, 70
81,93
76, 88, 100
IN
Power
Ground
Power
Ground
H: Normal operation,
L: Power down (all outputs are pulled to ground)
Power Supply Pins for TTL outputs and digital circuitry.
Ground Pins for TTL outputs and digital circuitry.
Power Supply Pins for LVDS inputs.
Ground Pins for LVDS inputs.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
3
THine Electronics, Inc.
THC63LVD824 _Rev2.0
Pin Name
PLL VCC
PLL GND
Pin #
2
1
Type
Power
Ground
Description
Power Supply Pin for PLL circuitry.
Ground Pin for PLL circuitry.
Absolute Maximum Ratings
1
Supply Voltage (V
CC
)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Output Current
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10sec)
Maximum Power Dissipation @+25
°C
-0.3V ~ +4.0V
-0.3V ~ (V
CC
+ 0.3V)
-0.3V ~ (V
CC
+ 0.3V)
-0.3V ~ (V
CC
+ 0.3V)
-30mA ~ 30mA
+125
°C
-55
°C
~ +125
°C
+230
°C
1.0W
Electrical Characteristics
CMOS/TTL DC Specifications
V
CC
= 3.0V ~ 3.6V, Ta = -10
°C
~ +70
°C
Symbol
V
IH
V
IL
V
OH
V
OL
I
INC
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current
I
OH
= -2mA, -4mA (data)
I
OH
= -4mA, -8mA (clock)
I
OL
= 2mA, 4mA (data)
I
OL
= 4mA, 8mA (clock)
0V
≤
V
IN
≤
V
CC
Conditions
Min.
2.0
GND
2.4
Typ.
Max.
V
CC
0.8
Units
V
V
V
0.4
±
10
V
µA
LVDS Receiver DC Specifications
V
CC
= 3.0V ~ 3.6V, Ta = -10
°C
~ +70
°C
Symbol
V
TH
V
TL
I
INL
Parameter
Differential Input High Threshold
Differential Input Low Threshold
Input Current
Conditions
V
OC
= 1.2V
V
OC
= 1.2V
V
IN
= 2.4V / 0V
V
CC
= 3.6V
-100
±
20
Min.
Typ.
Max.
100
Units
mV
mV
µA
1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They
are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics”
specify conditions for device operation.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
4
THine Electronics, Inc.
THC63LVD824 _Rev2.0
Supply Current
V
CC
= 3.0V ~ 3.6V, Ta = -10
°C
~ +70
°C
Symbol
Parameter
Condition(*)
VESA SXGA (60Hz),
f
CLKOUT
= 54MHz
VESA UXGA (60Hz),
f
CLKOUT
= 81MHz
VESA SXGA (60Hz),
f
CLKOUT
= 54MHz
VESA UXGA (60Hz),
f
CLKOUT
= 81MHz
/PDWN = L
MODE<1:0>=LH
CL=8pF,
Vcc=3.3V
MODE<1:0>=LL
CL=8pF,
Vcc=3.3V
MODE<1:0>=LH
CL=8pF,
Vcc=3.3V
MODE<1:0>=LL
CL=8pF,
Vcc=3.3V
148
173
mA
µA
87
99
mA
85
97
mA
57
66
mA
Typ.
Max.
Units
Receiver Supply
I
RCCG
Current
(256 Gray Scale Pattern)
Receiver Supply
I
RCCW
Current
(Double Checker Pattern)
I
RCCS
Receiver Power Down
Supply Current
10
(*) VESA is a trademark of the Video Electronics Standards Association.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
5
THine Electronics, Inc.
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