HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT70V07S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Commercial: 25/35/55ns (max.)
• Low-power operation
— IDT70V07S
Active: 450mW (typ.)
Standby: 5mW (typ.)
— IDT70V07L
Active: 450mW (typ.)
Standby: 5mW (typ.)
• IDT70V07 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/
S
= H for
BUSY
output flag on Master
M/
S
= L for
BUSY
input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• LVTTL-compatible, single 3.3V (±0.3V) power supply
• Available in 68-pin PGA, 68-pin PLCC, and a 64-pin
TQFP
DESCRIPTION:
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static
RAM. The IDT70V07 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
FUNCTIONAL BLOCK DIAGRAM
OE
L
OE
R
R/
CE
L
R/
W
L
CE
R
W
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
15
(1,2)
A
14L
A
0L
MEMORY
ARRAY
Address
Decoder
A
14R
A
0R
15
OE
L
R/
CE
L
W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
R/
OE
R
W
R
SEM
R
INT
R
SEM
L
(2)
INT
L
M/
S
(2)
2943 drw 01
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2943/3
6.37
1
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by
CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 450mW of power.
The IDT70V07 is packaged in a ceramic 68-pin PGA, a 68-
pin PLCC, and a 80-pin thin plastic quad flatpack (TQFP).
PIN CONFIGURATIONS
(1,2)
I/O
1L
I/O
0L
N/C
SEM
L
4
L
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
R/
9
8
7
6
5
3
A
14L
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
OE
L
W
CE
L
IDT70V07
J68-1
PLCC
TOP
VIEW(3)
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/
S
INT
R
BUSY
R
A
0R
A
1R
A
2R
A
3R
A
4R
2943 drw 02
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
OE
R
SEM
R
W
R
R/
CE
R
I/O
7R
N/C
A
14R
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
I/O
1L
I/O
0L
N/C
R/
L
SEM
L
INDEX
N/C
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
N/C
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
N/C
A
14L
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
N/C
N/C
OE
L
W
CE
L
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
70V07
PN80-1
TQFP
TOP
VIEW(3)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/
S
INT
R
BUSY
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
2943 drw 03
R/
R
I/O
7R
N/C
OE
R
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate the actual part marking.
6.37
SEM
R
N/C
A
14R
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
N/C
N/C
CE
R
W
2
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONT'D)
(1,2)
51
11
53
A
7L
55
A
9L
A
5L
52
A
6L
54
A
8L
50
A
4L
49
A
3L
48
A
2L
47
A
1L
46
44
42
A
0L
BUSY
L
M/
S
45
40
38
A
1R
INT
R
36
A
3R
35
A
4R
32
A
7R
30
A
9R
34
A
5R
33
A
6R
31
A
8R
10
43
41
39
37
INT
L
GND
BUSY
R
A
0R
A
2R
09
08
56
57
A
11L
A
10L
58
59
V
CC
A
12L
61
60
A
13L
62
07
IDT70V07
G68-1
68-PIN PGA
TOP VIEW
(3)
29
28
A
11R
A
10R
26
GND
27
A
12R
06
A
14L
63
05
SEM
L
65
CE
L
25
24
A
14R
A
13R
64
04
OE
L
R/
L
W
SEM
R
20
22
23
CE
R
03
67
66
I/O
0L
N/C
1
3
68
I/O
1L
I/O
2L
I/O
4L
2
4
I/O
5L
I/O
3L
B
C
5
7
9
11
13
15
GND I/O
7L
GND I/O
1R
V
CC
I/O
4R
6
I/O
6L
D
8
10
12
14
16
I/O
0R
I/O
2R
I/O
3R
I/O
5R
V
CC
E
F
G
H
J
OE
R
21
R/
R
W
02
18
19
I/O
7R
N/C
17
I/O
6R
K
01
A
INDEX
L
2943 drw 04
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port
Right Port
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2943 tbl 01
CE
L
R/
W
L
OE
L
A
0L
– A
14L
I/O
0L
– I/O
7L
CE
R
R/
W
R
OE
R
A
0R
– A
14R
I/O
0R
– I/O
7R
SEM
L
INT
L
BUSY
L
M/
S
V
CC
SEM
R
INT
R
BUSY
R
GND
6.37
3
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs
(1)
Outputs
CE
H
L
L
X
NOTE:
R/
W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
Mode
2943 tbl 02
1. A
0L
— A
14L
≠
A
0R
— A
14R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL
(1)
Inputs
Outputs
CE
H
H
L
R/
W
H
X
OE
L
X
X
SEM
L
L
L
I/O
0-7
DATA
OUT
DATA
IN
—
Read Data in Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Mode
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all I/O's (I/O
0
-I/O
7
). These eight semaphores are addressed by A
0
- A
2
.
2943 tbl 03
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial Unit
–0.5 to +4.6
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Ambient
Temperature
0°C to +70°C
GND
0V
V
CC
3.3V
±
0.3V
2943 tbl 05
T
A
T
BIAS
T
STG
I
OUT
0 to +70
–55 to +125
–55 to +125
50
°C
°C
°C
mA
RECOMMENDED DC OPERATING
CONDITIONS
(2)
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
–0.3
(1)
Typ.
3.3
0
—
—
Max. Unit
3.6
0
0.8
V
V
V
2943 tbl 06
V
CC
+0.3 V
NOTES:
2943 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.3V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of V
TERM
> Vcc
+ 0.3V.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.3V.
CAPACITANCE
(1)
(T
A
= +25°C, f = 1.0MHz)TQFP ONLY
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output
Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
NOTES:
2943 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.37
4
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 3.3V
±
0.3V)
IDT70V07S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 3.6V, V
IN
= 0V to V
CC
Min.
—
—
—
2.4
Max.
10
10
0.4
—
IDT70V07L
Min.
—
—
—
2.4
Max.
5
5
0.4
—
Unit
µA
µA
V
V
2943 tbl 08
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
NOTE:
1. At Vcc
≤
2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
(V
CC
= 3.3V
±
0.3V)
70V07X25
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports — TTL
Level Inputs)
Standby Current
(One Port — TTL
Level Inputs)
I
SB3
Full Standby Current
(Both Ports — All
CMOS Level Inputs)
Test
Condition
Version
COM’L.
S
L
S
L
S
L
Typ.
(2)
100
100
14
12
50
50
70V07X35
70V07X55
Max. Unit
140 mA
120
30
24
87
75
mA
Max. Typ.
(2)
170
140
30
24
95
85
90
90
12
10
45
45
Max. Typ.
(2)
140
120
30
24
87
75
90
90
12
10
45
45
f = f
MAX(3)
CE
= V
IL
, Outputs Open
SEM
= V
IH
CE
R
=
CE
L
= V
IH
SEM
R
=
SEM
L
= V
IH
CE
"A"
= V
IL
and
CE
"B"
= V
IH(5)
Active Port Outputs Open,
I
SB1
COM’L.
f = f
MAX(3)
I
SB2
COM’L.
mA
f = f
MAX
(3)
SEM
R
=
SEM
L
= V
IH
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Open
f = f
MAX(3)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
=
SEM
L
> V
CC
- 0.2V
COM’L.
S
L
1.0
0.2
6
3
1.0
0.2
6
3
1.0
0.2
6
3
mA
I
SB4
Full Standby Current
(One Port — All
CMOS Level Inputs)
COM’L.
S
L
60
60
90
80
55
55
85
74
55
55
85
74
mA
NOTES:
2943 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. V
CC
= 3.3V, T
A
= +25°C, and are not production tested. I
CCDC
= 80mA (Typ.)
3. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / t
RC,
and using “AC Test Conditions”
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.37
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
