CX28224/5/9
Inverse Multiplexing for ATM (IMA) Family
Data Sheet
28229-DSH-001-B
January 2003
Ordering Information
Model Number
CX28224
CX28225
CX28229
Manufacturing Part
Number
28224-14
28225-14
28229-14
Product
Revision
D
D
D
Package
256-pin, 17 mm BGA
256-pin, 17 mm BGA
256-pin, 17 mm BGA
Operating Temperature
–40
°
C to 85
°
C
–40
°
C to 85
°
C
–40
°
C to 85
°
C
Revision History
Revision
A
Level
Preliminary
Date
July 2001
Description
Preliminary A version. Note that this document was
also released as a preliminary version under the
document numbers 101265P1 and 101265P2.
Preliminary B version.
Removed all references to PLCP and updated some of
the bit descriptions.
Restructured and enhanced document to include more
IMA related information.
Updated Ordering Information and a few register
descriptions to reflect the CX28229-13 part.
Updated to reflect the -14 part. Section 8, Electrical
and Mechanical Specifications, improved and noted
with change bars.
Revised document number to reflect new numbering
system: new document number is 28229-DSH-001-B.
Removed Prelimary document designations. Replaced
hysteresis references with TTL levels in
Table 8-16.
B
C
D
E
F
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
September 2001
September 2001
April 2002
May 2002
September 2002
A
Released
January 2003
© 2001, 2002,
Mindspeed Technologies™, a Conexant business
All Rights Reserved.
Information in this document is provided in connection with Mindspeed Technologies (“Mindspeed”) products. These materials are provided by
Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no responsibility for errors or
omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed
makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to its specifications and product descriptions.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Mindspeed’s Terms and Conditions of Sale for such products, Mindspeed assumes no liability whatsoever.
THESE MATERIALS ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE
AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR
OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF
THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE
LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST
REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.
Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or selling
Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from
such improper use or sale.
The following are trademarks of Conexant Systems, Inc.: Mindspeed Technologies™, the Mindspeed™ logo, and “Build It First”™. Product
names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and
names are the property of their respective owners.
For additional disclaimer information, please consult Mindspeed Technologies Legal Information posted at
www.mindspeed.com
which is
incorporated by reference.
28229-DSH-001-B
Mindspeed Technologies
™
CX28224/5/9
Inverse Multiplexing for ATM (IMA) Family
The CX2822x family of devices provides system designers with a complete integrated
Distinguishing Features
IMA solution for up to 32 ports. All devices include a Transmission Convergence
!
Complete IMA solution in a single package
block to perform cell delineation, on-board RAM to meet ATM forum requirements
"
2 port, CX28224, 17mm BGA
"
4 port, CX28225, 17mm BGA
for differential delay compensation and a dual mode (UTOPIA or Serial) PHY layer
"
8/32 port, CX28229, 17mm BGA
interface.
Source code for all required software functions is available from Mindspeed. Since
all processing intensive functions are performed in hardware, they require only
minimal overhead from the system processor.
The TC block is capable of bit level cell delineation, which allows for direct connection
DSL serial data streams without a frame sync pulse. Individual ports can be operated
in a 'pass thru' mode without the IMA overhead.
The CX28229 provides direct connection to 8 serial links or can be expanded to a 32
port IMA using the PHY side UTOPIA bus and external TC devices such as the
RS8228. In addition, an external memory bus allows the differential delay memory to
access up to 2 Mbytes of external RAM.
!
!
!
!
!
!
!
!
!
Field tested software available
Supports up to 32 ports using external TC
PHYs
Up to 16 IMA groups
Supports the IMA standard requirements
for 25 ms differential delay with 256K
Internal memory
Memory expandable to 2 M bytes via
external bus (CX28229 only)
UTOPIA level 2 interfaces
Glueless interface to Mindspeed Framers
Octet or Bit level cell delineation
Variable link data rates (64K–3.072 Mb/s)
Functional Block Diagram
CX28229
External Memory Interface
TC Block
ATMmux[7,6] = 10 and
PhyIntFcSel pin = high
cell processor
cell processor
TC BLOCK UTOPIA INTERFACE
Line interface 0
Line interface 1
ATMmux[7,6] = 10
ATMmux[7,6] = 01
RX FIFO
PHY layer
UTOPIA 2 interface
Differential Delay
memory interface
Rx Block
ATMmux[7,6] = 01 and
PhyIntFcSel pin = Low
cell processor
Line interface 4
PhyIntFcSel Pin
high
cell processor
cell processor
cell processor
Line interface 5
Line interface 6
Line interface 7
IMA
Engine
Tx Block
Control
Registers
Status
Registers
Clock
interface
OneSec
IMA clocks
IMA_SysClk
IMA_RefClk
JTAG
Micro interface
Micro
Clocks
OneSecIO
TxTRL[0]
TxTRL[1]
MicroClk
28229-DSH-001-B
Mindspeed Technologies
™
8 KHzIn
PhyIntFcSel pin tied low
TC
Counters
TC Status
Registers
TC Control
Registers
Phy SIDE INTERFACE PINS
TX FIFO
low
ATM LAYER UTOPIA INTERFACE PINS
Internal
256Kx8
SRAM
RX FIFO
TX FIFO
IMA Block
0
extmemsel pin
cell processor
cell processor
Line interface 2
Line interface 3
1
PhyIntFcSel pin tied high
ATM layer
UTOPIA 2 interface
iii
IMA Features
!
!
!
Cell Delineation Section
!
UTOPIA Interfaces
!
!
!
!
!
!
!
!
Field proven design
All software available
Supports variable link data rates (64K–
3.072 Mb/s)
Internal memory
Connects directly to the Mindspeed
SARs for inexpensive CPE solutions
CX28224 2 ports
CX28225 4 ports
CX28229 32 ports
"
Memory expandable to 2 M bytes via
external bus
"
Up to 16 independent groups (using
external PHYs):
Each group can have up to 8 links.
Supports IMA versions 1.0 and 1.1
Fractional T1/E1
!
!
!
!
Supports ATM cell interface for:
"
Circuit-based physical layer
"
Cell-based physical layer
Performs single-bit HEC correction and
single- or multiple-bit detection
Inserts headers and generates HEC
Direct connection to external
Mindspeed components for:
"
T1/E1
"
xDSL
"
General purpose mode
Byte-level or bit-level cell delineation
!
UTOPIA Level 2 Interface to ATM Layer:
"
8/16 bit operation
"
50 MHz
PHY-side UTOPIA Interface:
"
8-bit UTOPIA Level 2
"
Supports 32 ports via dual CLAV
and Enable lines
Counters/Status Register Section
!
!
!
!
Control and Status
Microprocessor Interface
!
!
!
!
!
!
!
Asynchronous SRAM-like interface
mode
Synchronous, glueless Bt8233/RS8234
SAR interface mode
8-bit data bus
Open-drain interrupt output
Open-drain ready output
8–33 MHz operation
All control registers are read/write
Summary interrupt indications
Configuration of interrupt enables
One-second counter latching
Counters for:
"
LOCD events
"
Corrected HEC errors
"
Uncorrected HEC errors
"
Transmitted cells
"
Matching received cells
"
Non-matching received cells
28229-DSH-001-B
Mindspeed Technologies
™
iv
Contents
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
1
Introduction to IMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
Introduction To Inverse Multiplexing for ATM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.1 IMA Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.2 IMA Control Protocol Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.1.3 Link State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.1.4 Transmit Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.1.5 Differential Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.2.1 Software Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.2 Configuration (CF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.3 Diagnostics (DG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.4 Failure Monitoring (FM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.5 Performance Monitoring (PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.6 Group State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2
2
CX2822x Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram and Definitions (UTOPIA-to-UTOPIA Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram and Definitions (UTOPIA-to-Serial Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stand Alone Cell Delineation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source Loopback (UTOPIA-to-Serial Configuration Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Far-End Line Loopback (Serial Configuration Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2-3
2-18
2-34
2-35
2-36
2-37
2-37
3
IMA Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 T1/E1 Using Internal Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1.1 Using IMA_SysClk as the Transmit Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1.2 Using IMA_RefClk as the Transmit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 DSL/T1/E1 Using UTOPIA-to-UTOPIA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4
3-4
3-4
3-6
3-8
28229-DSH-001-B
Mindspeed Technologies
™
v
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