Freescale Semiconductor
Technical Data
Document Number: MPC8379EEC
Rev. 2, 10/2009
MPC8379E
™
PowerQUICC II Pro Processor
Hardware Specifications
This document provides an overview of the MPC8379E
PowerQUICC™ II Pro processor features, including a block
diagram showing the major functional components. The
device is a cost-effective, low-power, highly integrated host
processor that addresses the requirements of several printing
and imaging, consumer, and industrial applications,
including main CPUs and I/O processors in printing systems,
networking switches and line cards, wireless LANs
(WLANs), network access servers (NAS), VPN routers,
intelligent NIC, and industrial controllers. The MPC8379E
extends the PowerQUICC™ family, adding higher CPU
performance, additional functionality, and faster interfaces
while addressing the requirements related to time-to-market,
price, power consumption, and package size.
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 16
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 22
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Enhanced Secure Digital Host Controller (eSDHC) . 42
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 67
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 77
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
System Design Information . . . . . . . . . . . . . . . . . . 108
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 110
Document Revision History . . . . . . . . . . . . . . . . . . 113
1
Overview
The MPC8379E incorporates the e300c4s core, which
includes 32 Kbytes of L1 instruction and data caches and
on-chip memory management units (MMUs). The device
offers two enhanced three-speed 10, 100, 1000 Mbps
Ethernet interfaces, a DDR1/DDR2 SDRAM memory
controller, a flexible, a 32-bit local bus controller, a 32-bit
PCI controller, an optional dedicated security engine, a USB
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© Freescale Semiconductor, Inc., 2009. All rights reserved.
Overview
2.0 dual-role controller, a programmable interrupt controller, dual I
2
C controllers, a 4-channel DMA
controller, an enhanced secured digital host controller, and a general-purpose I/O port. The block diagram
of the MPC8379E is shown in
Figure 1.
MPC8379E
DUART
Dual I
2
C
Timers
GPIO
SPI
Interrupt
Controller
e300 Core
32-Kbyte
D-Cache
32-Kbyte
I-Cache
DDR1/DDR2
SDRAM
Controller
Security
Enhanced
Local Bus
USB 2.0
Hi-Speed
DMA
PCI
Host
Device
eTSEC
RGMII, RMII,
RTBI, MII
eTSEC
RGMII, RMII,
RTBI, MII
SATA
PHY
PHY
PHY
PHY
Figure 1. MPC8379E Block Diagram and Features
The following features are supported in the MPC8379E:
• e300c4s core built on Power Architecture™ technology with 32-Kbyte instruction cache and
32-Kbyte data cache, a floating point unit, and two integer units
• DDR1/DDR2 memory controller supporting a 32/64-bit interface
• Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation
• 32-bit local bus interface running up to 133-MHz
• USB 2.0 (full/high speed) support
• Power management controller for low-power consumption
• High degree of software compatibility with previous-generation PowerQUICC processor-based
designs for backward compatibility and easier software migration
• Optional security engine provides acceleration for control and data plane security protocols
The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive
cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator
provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.
MPC8379E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
2
Freescale Semiconductor
Overview
In addition to the security engine, a new high-speed interface such as SATA is included.
Table 1
compares
the differences between MPC837xE derivatives and provides the number of ports available for each
interface.
Table 1. High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E
Descriptions
SGMII
PCI Express®
SATA
MPC8377E
0
2
2
MPC8378E
2
2
0
MPC8379E
0
0
4
1.1
DDR Memory Controller
The DDR1/DDR2 memory controller includes the following features:
• Single 32- or 64-bit interface supporting both DDR1 and DDR2 SDRAM
• Support for up to 400-MHz data rate
• Support up to 4 chip selects
• 64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with
×8/×16/×32
data ports (no
direct
×4
support)
• Support for up to 32 simultaneous open pages
• Supports auto refresh
• On-the-fly power management using CKE
• 1.8-/2.5-V SSTL2 compatible I/O
1.2
USB Dual-Role Controller
The USB controller includes the following features:
• Supports USB on-the-go mode, including both device and host functionality, when using an
external ULPI (UTMI + low-pin interface) PHY
• Complies with
USB Specification, Rev. 2.0
• Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
• Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation;
low-speed operation is supported only in host mode
• Supports UTMI + low pin interface (ULPI)
MPC8379E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
3
Overview
1.3
Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)
The eTSECs include the following features:
• Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI
• Two controllers conform to IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z,
IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588™ standards
• Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating
mode
• MII management interface for external PHY control and status
1.4
Integrated Programmable Interrupt Controller (IPIC)
The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a
flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with
the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources.
Interrupts can also be redirected to an external interrupt controller.
1.5
Power Management Controller (PMC)
The power management controller includes the following features:
• Provides power management when the device is used in both host and agent modes
• Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states
• Support for PME generation in PCI agent mode, PME detection in PCI host mode
• Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host)
• Supports MPC8349E backward-compatibility mode
1.6
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC
family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit.
1.7
DMA Controller, Dual I
2
C, DUART, Enhanced Local Bus Controller
(eLBC), and Timers
The device provides an integrated four-channel DMA controller with the following features:
• Allows chaining (both extended and direct) through local memory-mapped chain descriptors
(accessible by local masters)
• Supports misaligned transfers
MPC8379E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
4
Freescale Semiconductor
Overview
There are two I
2
C controllers. These synchronous, multi-master buses can be connected to additional
devices for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.
The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides
a seamless interface to many types of memory devices and peripherals. The memory controller is
responsible for controlling eight memory banks shared by a NAND Flash control machine (FCM), a
general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As
such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EPROM, NAND Flash,
EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other
peripherals. The eLBC external address latch enable (LALE) signal allows multiplexing of addresses with
data signals to reduce the device pin count.
The enhanced local bus controller also includes a number of data checking and protection features, such
as data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle
is terminated within a user-specified period. The local bus can operate at up to 133 MHz.
The system timers include the following features: periodic interrupt timer, real time clock, software
watchdog timer, and two general-purpose timer blocks.
1.8
Security Engine
The optional security engine is optimized to handle all the algorithms associated with IPSec,
IEEE 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto
execution units (EUs). The execution units are:
• Data encryption standard execution unit (DEU), supporting DES and 3DES
• Advanced encryption standard unit (AESU), supporting AES
• Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any
algorithm
• One crypto-channel supporting multi-command descriptor chains
1.9
PCI Controller
The PCI controller includes the following features:
•
PCI Specification Revision 2.3
compatible
• Single 32-bit data PCI interface operates at up to 66 MHz
• PCI 3.3-V compatible (not 5-V compatible)
• Support for host and agent modes
• On-chip arbitration, supporting 5 external masters on PCI
• Selectable hardware-enforced coherency
MPC8379E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
5
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