NB7VQ1006M
1.8 V / 2.5 V 10 Gbps
Equalizer Receiver with 1:6
Differential CML Outputs
Multi-Level Inputs W / Internal Termination
Description
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The NB7VQ1006M is a high performance differential 1:6 CML
fanout buffer with a selectable Equalizer receiver. When placed in
series with a Data path operating up to 10 Gb/s, the NB7VQ1006M
will compensate the degraded data signal transmitted across a FR4
PCB backplane or cable interconnect and output six identical CML
copies of the input signal. Therefore, the serial data rate is increased by
reducing Inter-Symbol Interference (ISI) caused by losses in copper
interconnect or long cables.
The EQualizer ENable pin (EQEN) allows the IN/IN inputs to either
flow through or bypass the Equalizer section. Control of the Equalizer
function is realized by setting EQEN; When EQEN is set Low, the
IN/IN inputs bypass the Equalizer. When EQEN is set High, the IN/IN
inputs flow through the Equalizer. The default state at startup is LOW.
As such, the NB7VQ1006M is ideal for SONET, GigE, Fiber Channel,
Backplane and other Data distribution applications.
The differential inputs incorporate internal 50
W
termination
resistors that are accessed through the VT pin. This feature allows the
NB7VQ1006M to accept various logic level standards, such as
LVPECL, CML or LVDS. This feature provides transmission line
termination at the receiver, eliminating external components. The
outputs have the flexibility of being powered by either a 1.8 V or 2.5 V
supply.
The NB7VQ1006M is a member of the GigaComm™ family of high
performance Clock/Data products.
Features
QFN−24
MN SUFFIX
CASE 485L
MARKING DIAGRAM*
24
1
NB7V
Q1006M
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note
AND8002/D.
SIMPLIFIED BLOCK DIAGRAM
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Data Rate > 10 Gbps
Maximum Input Clock Frequency > 7.5 GHz
Backplane and Cable Interconnect Compensation
225 ps Typical Propagation Delay
30 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV Peak-to-Peak, Typical
Operating Range: V
CC
= 1.71 V to 2.625 V, GND = 0 V
Internal Input Termination Resistors, 50
W
QFN−24 Package, 4 mm x 4 mm
−40°C
to +85°C Ambient Operating Temperature
This Device is Pb-Free, Halogen Free and is RoHS Compliant
EQ
ORDERING INFORMATION
Device
NB7VQ1006MMNG
NB7VQ1006MMNTXG
Package
QFN−24
(Pb-Free)
Shipping†
92 Units / Tube
QFN−24
3000 Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure,
BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
August, 2016
−
Rev. 3
1
Publication Order Number:
NB7VQ1006M/D
NB7VQ1006M
CML Outputs
Multi−Level Inputs
LVPECL, LVDS, CML
IN
VT
IN
50
W
Q0
Q0
Q1
50
W
0
Q1
Q2
Q2
EQ
Q3
1
Q3
Q4
EQEN
(Equalizer Enable)
Q4
75 kW
Q5
Q5
Figure 1.
Detailed Block Diagram of NB7VQ1006M
Table 1. EQUALIZER ENABLE FUNCTION
EQEN
0
1
Function
IN/IN Inputs Bypass the EQualizer Section
IN/IN Inputs Flow through the EQualizer Section
GND
24
VCC
IN
IN
VT
EQEN
VCC
1
2
3
4
5
6
7
GND
23
22
21
20
GND
Q0
Q0
Q1
Q1
Exposed Pad
(EP)
19
18
17
VCCO
Q2
Q2
Q3
Q3
VCCO
NB7VQ1006M
16
15
14
13
8
Q5
9
Q5
10
Q4
11
Q4
12
GND
Figure 2. QFN−24 Lead Pinout
(Top View)
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2
NB7VQ1006M
Table 2. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
−
Name
VCC
IN
IN
VT
EQEN
VCC
GND
Q5
Q5
Q4
Q4
GND
VCCO
Q3
Q3
Q2
Q2
VCCO
GND
Q1
Q1
Q0
Q0
GND
EP
−
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
LVCMOS Input
LVPECL, CML,
LVDS Input
LVPECL, CML,
LVDS Input
I/O
Positive Supply Voltage for the Core Logic
Non-inverted Differential Clock/Data Input. (Note 1)
Inverted Differential Clock/Data Input. (Note 1)
Internal 50
W
Termination Pin for IN and IN
Equalizer Enable Input; pin will default LOW when left open (has internal pull-down resistor)
Positive Supply Voltage for the Core Logic
Negative Supply Voltage
Inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Non-inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Non-inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Negative Supply Voltage
Positive Supply Voltage for the pre-amplifier and output buffer
Inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Non-inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Non-inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Positive Supply Voltage for the pre-amplifier and output buffer
Negative Supply Voltage
Inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Non-inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Non-inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
.
Negative Supply Voltage
The Exposed Pad (EP) on the QFN−24 package bottom is thermally connected to the die for im-
proved heat transfer out of package. The exposed pad must be attached to a heat-sinking con-
duit. The pad is electrically connected to GND and is recommended to be electrically connected
to GND on the PC board.
Description
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN, then the device will be susceptible to self-oscillation.
2. All VCC, VCCO and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation.
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NB7VQ1006M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note
AND8003/D.
Oxygen Index: 28 to 34
Value
> 4 kV
> 200 V
Level 1
UL 94 V−0 @ 0.125 in
244
Table 4. MAXIMUM RATINGS
Symbol
V
CC
,
V
CCO
V
I
V
INPP
I
IN
I
OUT
T
A
T
stg
q
JA
Positive Power Supply
Input Voltage
Differential Input Voltage |IN−IN|
Input Current Through R
T
(50
W
Resistor)
Output Current Through R
T
(50
W
Resistor)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient) (Note 1)
TGSD 51−6 (2S2P Multilayer Test Board) with Filled
Thermal Vias
Thermal Resistance (Junction-to-Case)
Wave Solder (Pb-Free)
0 lfpm
500 lfpm
Standard Board
QFN−24
QFN−24
QFN−24
Parameter
Condition 1
GND = 0 V
GND = 0 V
Condition 2
Rating
3.0
−0.5
to V
CC
+ 0.5
1.89
$40
$40
−40
to +85
−65
to +150
37
32
11
265
Unit
V
V
V
mA
mA
°C
°C
°C/W
q
JC
T
sol
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7VQ1006M
Table 5. DC CHARACTERISTICS
−
CML OUTPUT
(V
CC
= V
CCO
= 1.71 V to 2.625 V; GND = 0 V T
A
=
−40°C
to 85°C)
Symbol
Characteristic
Min
Typ
Max
Unit
POWER SUPPLY CURRENT
(Inputs and Outputs open)
I
CC
I
CCO
Power Supply Current, Core Logic
V
CC
= 2.5V
V
CC
= 1.8V
Power Supply Current, Outputs
V
CCO
= 2.5V
V
CCO
= 1.8V
100
85
180
150
115
95
200
175
mA
CML OUTPUTS
(Notes 1 and 2) (Figure 10)
V
OH
Output HIGH Voltage
V
CCO
= 2.5 V
V
CCO
= 1.8 V
Output LOW Voltage
V
CCO
= 2.5V
V
CCO
= 2.5V
V
CCO
= 1.8V
V
CCO
= 1.8V
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
−
V
ILD
)
Input HIGH Current
Input LOW Current
V
CCO
– 40
2460
1760
V
CCO
– 600
1900
V
CCO
– 525
1275
V
CCO
– 10
2490
1790
V
CCO
– 500
2000
V
CCO
– 425
1375
V
CCO
2500
1800
V
CCO
– 400
2100
V
CCO
– 300
1500
mV
V
OL
mV
DATA/CLOCK INPUTS (IN, IN)
(Note 3) (Figures 6 & 7)
V
IHD
V
ILD
V
ID
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
R
TIN
R
TOUT
1100
GND
100
−150
−150
30
−40
V
CC
V
CC
−
100
1200
+150
+150
mV
mV
mV
mA
mA
CONTROL INPUTS
(EQEN)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
V
CC
x 0.65
GND
−150
−150
25
10
V
CC
V
CC
x 0.35
+150
+150
mV
mV
mA
mA
TERMINATION RESISTORS
Internal Input Termination Resistor
Internal Output Termination Resistor
45
45
50
50
55
55
W
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. CML outputs loaded with 50
W
to V
CC
for proper operation.
2. Input and output parameters vary 1:1 with V
CC/
V
CCO
.
3. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
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