Revision 4.1
January 2008
VSC056 Data Sheet
Enhanced Two-Wire Serial Backplane Controller
F
EATURES
•
•
•
•
•
•
Up to 64 bits of user-definable, bidirectional
general-purpose inputs and outputs
Integrated port bypass, clock recovery and signal
detect support for up to 16 drives
Eight programmable fan speed monitoring inputs
Eight programmable pulse-width modulated fan
control outputs
Up to 32 programmable input-to-output bypass pairs
Two clock input ranges: 8.0 MHz to 12.5 MHz
(external crystal or external clock source) and
32.0 MHz to 75.0 MHz (external clock source)
Selectable direct LED drive flashing capability
Pin-programmable addressing for up to 16 devices
on a single serial bus
5-V tolerant high current I/O, Slave mode two-wire
serial interface and interrupt output
Ten programmable LED pulse train circuits
One 24-bit general-purpose timer (supports a
timeout greater than four seconds with a 12.5 MHz
core clock)
•
•
•
•
Up to 16 subaddressed Master mode two-wire serial
interface ports
External reset of the slave two-wire serial core
Enhanced fan speed monitor input filters
20% of package pins are power and ground for
excellent noise immunity and long-term reliability
A
PPLICATIONS
•
•
•
•
•
•
•
•
•
Enterprise storage environments
Storage Area Network (SAN) appliances
Network Attached Storage (NAS) systems
Fabric Attached Storage (FAS) systems
Rack-mounted servers with RAID
JBOD arrays
Disk-based backup storage
Near-line storage replacement systems
Fixed-content storage systems
•
•
•
•
•
To order the VSC056 device, see
“Ordering Information,”
page 134.
G
ENERAL
D
ESCRIPTION
The VSC056 device is an I/O-intensive peripheral device that is intended to be part of a cost-effective Fibre Channel
Arbitrated Loop (FC-AL), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), or Serial ATA
(SATA) enclosure management solution. The device contains an address-programmable two-wire serial interface, a
block of control and status registers, I/O port control logic, specialized port bypass control logic, and a clock-
generation block.
Along with an external crystal, the device can be configured to support up to 64 bits of general-purpose I/O; or 16 bits
of general-purpose I/O, 32 bits of port bypass control (16 pairs supporting 16 drives), eight fan speed monitoring
inputs, and eight pulse-width modulated general-purpose control outputs.
The VSC056 supports various combinations of individual port bypass circuit (PBC), clock recovery unit (CRU), and
signal detect unit (SDU) functions, as well as integrated solutions. The control register portion of the device allows
the user to individually program each I/O pin as an input, an output, or an open-drain or open-source output.
Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
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VSC056
Data Sheet
Additional control features include: selectable flash rates for direct LED drive, input edge detection for interrupt
generation, input to output bypass capability, fan speed monitoring control, and pulse-width modulated output
control. Support for sub-addressing additional two-wire serial slave devices using a set of seven control registers is
included. This capability allows up to 16 independent Master mode two-wire serial slave ports to be created using 32
of the I/O pins.
The addressing capability of the VSC056 includes three pins, which are used for device addressing, as well as one pin
that can be used to select two device type identifiers. Sixteen VSC056 devices can be used in a single two-wire serial
interface system.
Block Diagram
I/OPorts
P0.0
−
P0.7
P1.0
−
P1.7
P2.0
−
P2.7
P3.0
−
P3.7
P4.0
−
P4.7
P5.0
−
P5.7
P6.0
−
P6.7
P7.0
−
P7.7
OSCI
OSCO
CKSEL0
CKSEL1
CKSEL2
SYNCEN
SY NC#
Clock
Generator
andDiv iders
Pulse-Width
Modulation
Control
Fan Speed
Sensors
I/OControl
andLED
Flashing
Port By pass
Control
SDA
SCL
A2
−
A0
ASEL
INT#
RESET
Two-Wire
Slav e
Interf ace
Interrupt Priority and Control
Power-On
Reset
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Revision 4.1
January 2008
VSC056
Data Sheet
T
YPICAL
A
PPLICATIONS
FC-AL Drive Enclosure Configuration
●
●
Basic port bypass configuration
Support for up to 128 drives: Backplane Controller supports up to two sets of CRU/SDU functions and drives,
and 16 Backplane Controllers can be attached simultaneously to the serial bus
Four-drive implementation is shown below; four-channel PBC with two CRU/SDU functions and general-
purpose I/O lines for drive control and status, and other enclosure control functions.
●
Figure 1. Single Loop, Single Controller with Four Drives
Copper or
Optics
Local I/O (x8)
PBC_EN
VSC7142
VSC120
X24C16
EEPROM
Embedded
Controller
Flash
Memory
Driv e Bay 1
PBC_EN1
PBC_EN2
PBC_EN3
PBC_EN4
Two-Wire Serial
Interf ace
Driv e Bay 2
VSC7147
Driv e Bay 3
Driv e Bay 4
Temperature
Sensor
(LM75)
VSC056
Enhanced Backplane
Controller
LEDs (x8)
Power
Supplies
Fans (x4)
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Revision 4.1
January 2008
VSC056
Data Sheet
General-Purpose I/O Configuration
●
●
Controlled by general-purpose microcontroller with two-wire serial interface
Support for up to 1024 I/O lines: Backplane controller supports up to 64 I/O lines and 16 backplane controllers
can be simultaneously attached to the serial bus
Four-backplane controller implementation is shown here with shared open-drain interrupt
●
Figure 2. Four Backplane Controllers, 256 Bidirectional I/O Lines
Microcontroller
with
Two-Wire Serial
Interf ace
Two-Wire Serial Interf ace
Interrupt (optional)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
VSC056
Enhanced
Backplane
Controller
VSC056
Enhanced
Backplane
Controller
VSC056
Enhanced
Backplane
Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
VSC056
Enhanced
Backplane
Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
(x8)
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Revision 4.1
January 2008
VSC056
Data Sheet
Contents
General Description.....................................................................................................
Features ........................................................................................................................
Applications .................................................................................................................
Typical Applications ....................................................................................................
Revision History...........................................................................................................
1
2
1
1
1
3
9
Introduction ....................................................................................................... 10
Functional Descriptions ................................................................................... 11
2.1
2.2
2.3
2.4
2.5
Two-Wire Serial Interface ............................................................................................................11
Control Registers .........................................................................................................................11
I/O Logic ......................................................................................................................................13
Clock Generator ..........................................................................................................................13
Power-on Reset ...........................................................................................................................14
3
Registers ............................................................................................................ 15
3.1
3.2
Control Registers .........................................................................................................................15
Control Register Definitions .........................................................................................................21
3.2.1
00h: General-Purpose I/O Port 0 Data (GPD0) .............................................................21
3.2.2
01h: General-Purpose I/O Port 1 Data (GPD1) .............................................................22
3.2.3
02h: General-Purpose I/O Port 2 Data (GPD2) .............................................................22
3.2.4
03h: General-Purpose I/O Port 3 Data (GPD3) .............................................................23
3.2.5
04h: General-Purpose I/O Port 4 Data (GPD4) .............................................................23
3.2.6
05h: General-Purpose I/O Port 5 Data (GPD5) .............................................................24
3.2.7
06h: General-Purpose I/O Port 6 Data (GPD6) .............................................................24
3.2.8
07h: General-Purpose I/O Port 7 Data (GPD7) .............................................................25
3.2.9
10h: I/O Port 0 Data Direction (DDP0) ...........................................................................25
3.2.10 11h: I/O Port 1 Data Direction (DDP1) ...........................................................................26
3.2.11 12h: I/O Port 2 Data Direction (DDP2) ...........................................................................26
3.2.12 13h: I/O Port 3 Data Direction (DDP3) ...........................................................................27
3.2.13 14h: I/O Port 4 Data Direction (DDP4) ...........................................................................27
3.2.14 15h: I/O Port 5 Data Direction (DDP5) ...........................................................................28
3.2.15 16h: I/O Port 6 Data Direction (DDP6) ...........................................................................28
3.2.16 17h: I/O Port 7 Data Direction (DDP7) ...........................................................................29
3.2.17 20h: Port Bypass Control 0 (PBC0) ...............................................................................30
3.2.18 21h: Port Bypass Control 1 (PBC1) ...............................................................................31
3.2.19 22h: Port Bypass Control 2 (PBC2) ...............................................................................32
3.2.20 23h: Port Bypass Control 3 (PBC3) ...............................................................................33
3.2.21 24h: Port Bypass Control 4 (PBC4) ...............................................................................34
3.2.22 25h: Port Bypass Control 5 (PBC5) ...............................................................................35
3.2.23 26h: Port Bypass Control 6 (PBC6) ...............................................................................36
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Revision 4.1
January 2008
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