ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8624I is a high performance, 1-to-5
Differential-to-HSTL zero delay buffer. The ICS8624I
has two selectable clock input pairs. The CLK0,
nCLK0 and CLK1, nCLK1 pair can accept most standard
differential input levels. The VCO operates at a frequency
range of 250MHz to 630MHz. Utilizing one of the outputs
as feedback to the PLL, output frequencies up to 630MHz
can be regenerated with zero delay with respect to the
input. Dual reference clock inputs support reduntant clock
or multiple reference applications..
F
EATURES
•
Fully integrated PLL
•
Five differential HSTL compatible outputs
•
Selectable differential CLKx, nCLKx input pairs
•
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
•
Output frequency range: 31.25MHz to 630MHz
•
Input frequency range: 31.25MHz to 630MHz
•
VCO range: 250MHz to 630MHz
•
External feedback for “zero delay” clock regeneration
•
Cycle-to-cycle jitter: 35ps (maximum)
•
Output skew: 50ps (maximum)
•
Static phase offset: 30ps ±125ps
•
3.3V core, 1.8V output operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS-compliant
packages
B
LOCK
D
IAGRAM
Q0
nQ0
PLL_SEL
÷4, ÷8
0
1
1
Q3
nQ3
Q1
nQ1
0
Q2
nQ2
P
IN
A
SSIGNMENT
PLL_SEL
GND
GND
V
DDO
V
DDA
nQ4
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
32 31 30 29 28 27 26 25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
DD
nFB_IN
FB_IN
GND
GND
nQ0
Q0
V
DDO
V
DD
Q4
24
23
22
V
DDO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
DDO
PLL
Q4
nQ4
ICS8624I
21
20
19
18
17
SEL0
SEL1
MR
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
8624BYI
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1
REV. C JULY 30, 2010
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
Name
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Description
Determines the input and output frequency range noted in Table 3.
LVCMOS / LVTTL interface levels.
Determines the input and output frequency range noted in Table 3.
LVCMOS / LVTTL interface levels.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Clock select input. When LOW, selects CLK0, nCLK0. When HIGH, selects
CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Core supply pins.
Feedback input to phase detector for regenerating clocks with "zero delay".
Feedback input to phase detector for regenerating clocks with "zero delay".
Power supply ground.
Differential clock outputs. 50
Ω
typical output impedance.
HSTL interface levels.
Output supply pins.
Differential clock outputs. 50
Ω
typical output impedance.
HSTL interface levels.
Differential clock outputs. 50
Ω
typical output impedance.
HSTL interface levels.
Differential clock outputs. 50
Ω
typical output impedance.
HSTL interface levels.
Differential clock outputs. 50
Ω
typical output impedance.
HSTL interface levels.
Analog supply pin.
Selects between the PLL and clock as the input to the dividers.
Pullup
When HIGH, selects PLL. When LOW, selects reference clock.
LVCMOS / LVTTL interface levels.
to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8
9, 32
10
11
12, 13
28, 29
14, 15
16, 17,
24, 25
18, 19
20, 21
22, 23
26, 27
30
31
MR
V
DD
nFB_IN
FB_IN
GND
nQ0, Q0
V
DDO
nQ1, Q1
nQ2, Q2
nQ3, Q3
nQ4, Q4
V
DDA
PLL_SEL
Input
Power
Input
Input
Power
Output
Power
Output
Output
Output
Output
Power
Input
Pulldown
Pullup
Pulldown
NOTE 1:
Pullup
and
Pulldown
refer
8624BYI
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2
REV. C JULY 30, 2010
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL1
0
0
1
1
SEL0
0
1
0
1
Reference Frequency Range (MHz)*
250 - 630
125 - 315
62.5 - 157.5
31.25 - 78.75
Outputs
PLL_SEL = 1
PLL Enable Mode
Q0:Q4, nQ0:nQ4
÷1
÷1
÷1
÷1
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
T
ABLE
3B. PLL B
YPASS
F
UNCTION
T
ABLE
Inputs
SEL1
0
0
1
1
SEL0
0
1
0
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q0:Q4, nQ0:nQ4
÷4
÷4
÷4
÷8
8624BYI
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3
REV. C JULY 30, 2010
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
0
Test Conditions
Minimum
3.135
3.135
1.6
Typical
3.3
3.3
1.8
Maximum
3.465
3.465
2.0
120
15
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
SEL0, SEL1,
CLK_SEL, MR
PLL_SEL
SEL0, SEL1,
CLK_SEL, MR
PLL_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
Input Low Current
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
0.5
V
CMR
NOTE 1: For single ended applications, the maximum input voltage for CLKx, nCLKx is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
8624BYI
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4
REV. C JULY 30, 2010
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
4D. HSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
OX
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Test Conditions
Minimum
1.0
0
40
0.6
Typical
Maximum
1.4
0.4
60
1.1
Units
V
V
%
V
V
SWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
IN
Parameter
Input Frequency
CLK0, nCLK0,
CLK1, nCLK1
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
31.25
Typical
Maximum
630
630
Units
MHz
MHz
T
ABLE
6A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
t(Ø)
Parameter
Output Frequency
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 5
Output Skew; NOTE 3, 5
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
Output Rise Time
Output Fall Time
20% to 80%
20% to 80%
300
300
IJ 630MHz
PLL_SEL = 3.3V
3.4
-95
3.9
30
Test Conditions
Minimum
Typical
Maximum
630
4.5
155
50
35
±50
1
70 0
700
Units
MHz
ns
ps
ps
ps
ps
ms
ps
ps
ps
t
sk(o)
t
jit(cc)
t
jit(Ø)
t
L
t
R
t
F
t
PW
Output Pulse Width
tPeriod/2 - 85 tPeriod/2 tPeriod/2+ 85
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal
across all conditions, when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
T
ABLE
6B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±10%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
Parameter
Cycle-to-Cycle Jitter; NOTE 1
Test Conditions
Minimum
Typical
Maximum
40
Units
ps
t
jit(cc)
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
8624BYI
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5
REV. C JULY 30, 2010
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