MIC26903
28V, 9A Hyper Light Load™
Synchronous DC/DC Buck Regulator
SuperSwitcher IIG™
General Description
The Micrel MIC26903 is a constant-frequency,
synchronous DC/DC buck regulator featuring adaptive on-
time control architecture. The MIC26903 operates over a
supply range of 4.5V to 28V. It has an internal linear
regulator which provides a regulated 5V to power the
internal control circuitry. MIC26903 operates at a constant
600kHz switching frequency in continuous conduction
mode and can be used to provide up to 9A of output
current. The output voltage is adjustable down to 0.8V.
Micrel’s Hyper Light Load™ architecture provides the same
high-efficiency and ultra-fast transient response as the
Hyper Speed Control™ architecture under medium to heavy
loads, but also maintains high efficiency under light load
conditions by transitioning to variable frequency,
discontinuous mode operation.
The MIC26903 offers a full suite of protection features to
ensure protection of the IC during fault conditions. These
include undervoltage lockout to ensure proper operation
under power-sag conditions, thermal shutdown, internal
soft-start to reduce the inrush current, foldback current
limit and “hiccup mode” short-circuit protection. The
MIC26903 includes a Power Good (PG) output to allow
simple sequencing.
All support documentation can be found on Micrel’s web
site at:
www.micrel.com.
Features
•
•
Hyper Light Load™ efficiency – up to 80% at 10mA
Hyper Speed Control™ architecture enables
−
High delta V operation (V
IN
= 28V and V
OUT
= 0.8V)
−
Small output capacitance
Input voltage range: 4.5V to 28V
Output current up to 9A
Up to 95% efficiency
Adjustable output voltage from 0.8V to 5.5V
±1% FB accuracy
Any Capacitor
TM
stable
−
zero-to-high ESR
600kHz switching frequency
Power Good (PG) output
Foldback current-limit and “hiccup” mode short-circuit
protection
Safe start-up into pre-biased loads
5mm
×
6mm MLF
®
package
–40°C to +125°C junction temperature range
•
•
•
•
•
•
•
•
•
•
•
•
Applications
•
Distributed power systems
•
Telecom/networking infrastructure
•
Printers, scanners, graphic cards and video cards
___________________________________________________________________________________________________________
Efficiency (V
IN
= 12V)
vs. Output Current
100
95
90
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
0.8V
Typical Application
EFFICIENCY (%)
85
80
75
70
65
60
55
50
0
3
6
9
V
IN
= 12V
12
OUTPUT CURRENT (A)
Hyper Speed Control, Hyper Light Load, SuperSwitcher II, and Any Capacitor are trademarks of Micrel, Inc.
MLF and
MicroLeadFrame
are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
July 2011
M9999-071311-A
Micrel, Inc.
MIC26903
Ordering Information
Part Number
MIC26903YJL
Voltage
Adjustable
Switching Frequency
600kHz
Junction Temperature
Range
–40°C to +125°C
Package
28-Pin 5mm
×
6mm MLF
®
Lead Finish
Pb-Free
Pin Configuration
28-Pin 5mm x 6mm MLF
®
(YJL)
Pin Description
Pin Number
1
3
4, 9, 10, 11, 12
Pin Name
PVDD
NC
SW
Pin Function
5V Internal Linear Regulator (Output): PVDD supply is the power MOSFET gate drive supply
voltage and created by internal LDO from V
IN
. When V
IN
< +5.5V, PVDD should be tied to PVIN
pins.
A 2.2µF ceramic capacitor from the PVDD pin to PGND (pin 2)
must be place next to the IC.
No Connect.
Switch Node (Output): Internal connection for the high-side MOSFET source and low-side
MOSFET drain. Due to the high speed switching on this pin, the SW pin should be routed away
from sensitive nodes.
Power Ground. PGND is the ground path for the MIC26903 buck converter power stage. The
PGND pins connect to the low-side N-Channel internal MOSFET gate drive supply ground, the
sources of the MOSFETs, the negative terminals of input capacitors, and the negative terminals of
output capacitors. The loop for the power ground should be as small as possible and separate
from the Signal ground (SGND) loop.
High-Side N-internal MOSFET Drain Connection (Input): The PV
IN
operating voltage range is from
4.5V to 26V. Input capacitors between the PVIN pins and the power ground (PGND) are required
and keep the connection short.
Boost (output): Bootstrapped voltage to the high-side N-channel MOSFET driver. A Schottky diode
is connected between the PVDD pin and the BST pin. A boost capacitor of 0.1μF is connected
between the BST pin and the SW pin. Adding a small resistor at the BST pin can slow down the
turn-on time of high-side N-Channel MOSFETs.
2, 5, 6, 7, 8, 21
PGND
13,14,15,
16,17,18,19
PVIN
20
BST
July 2011
2
M9999-071311-A
Micrel, Inc.
MIC26903
Pin Description (Continued)
Pin Number
Pin Name
Pin Function
Current Sense (Input): The CS pin senses current by monitoring the voltage across the low-side
MOSFET during the OFF-time. The current sensing is necessary for short circuit protection and zero
current cross comparator. In order to sense the current accurately, connect the low-side MOSFET
drain to SW using a Kelvin connection. The CS pin is also the high-side MOSFET’s output driver
return.
Signal ground. SGND must be connected directly to the ground planes. Do not route the SGND pin
to the PGND Pad on the top layer, see PCB layout guidelines for details.
Feedback (Input): Input to the transconductance amplifier of the control loop. The FB pin is regulated
to 0.8V. A resistor divider connecting the feedback to the output is used to adjust the desired output
voltage.
Power Good (Output): Open Drain Output. The PG pin is externally tied with a resistor to VDD. A
high output is asserted when V
OUT
>
92% of nominal.
Enable (Input): A logic level control of the output. The EN pin is CMOS-compatible. Logic high =
enable, logic low = shutdown. In the off state, supply current of the device is greatly reduced (typically
5µA). The EN pin should not be left open.
Power Supply Voltage (Input): Requires bypass capacitor to SGND.
5V Internal Linear Regulator (Output): VDD supply is the supply bus for the IC control circuit. VDD is
created by internal LDO from V
IN
. When V
IN
< +5.5V,
VDD should be tied to PVIN pins. A 1.0µF
ceramic capacitor from the VDD pin to SGND pins
must be place next to the IC.
22
CS
23
24
25
26
27
28
SGND
FB
PG
EN
VIN
VDD
July 2011
3
M9999-071311-A
Micrel, Inc.
MIC26903
Absolute Maximum Ratings
(1,2)
PV
IN
to PGND................................................
−0.3V
to +29V
V
IN
to PGND ....................................................−0.3V to PV
IN
PV
DD
, V
DD
to PGND .........................................
−0.3V
to +6V
V
SW
, V
CS
to PGND ..............................
−0.3V
to (PV
IN
+0.3V)
V
BST
to V
SW
........................................................
−0.3V
to 6V
V
BST
to PGND ..................................................
−0.3V
to 35V
V
FB
, V
PG
to PGND...............................
−0.3V
to (V
DD
+ 0.3V)
V
EN
to PGND ........................................
−0.3V
to (V
IN
+0.3V)
PGND to SGND ...........................................
−0.3V
to +0.3V
Junction Temperature .............................................. +150°C
Storage Temperature (T
S
).........................−65°C to +150°C
Lead Temperature (soldering, 10sec)........................ 260°C
Operating Ratings
(3)
Supply Voltage (PV
IN
, V
IN
)................................. 4.5V to 28V
PVDD, VDD Supply Voltage (PV
DD
, V
DD
)......... 4.5V to 5.5V
Enable Input (V
EN
) .................................................. 0V to V
IN
Junction Temperature (T
J
) ........................
−40°C
to +125°C
Maximum Power Dissipation......................................Note 4
Package Thermal Resistance
(4)
5mm x 6mm MLF
®
-24L (θ
JA
) .............................28°C/W
Electrical Characteristics
(5)
PV
IN
= V
IN
= V
EN
= 12V, V
BST
– V
SW
= 5V; T
A
= 25°C, unless noted.
Bold
values indicate
−40°C
≤
T
J
≤
+125°C.
Parameter
Power Supply Input
Input Voltage Range (V
IN
, PV
IN
)
Quiescent Supply Current
Shutdown Supply Current
V
DD
Supply Voltage
V
DD
Output Voltage
V
DD
UVLO Threshold
V
DD
UVLO Hysteresis
Dropout Voltage (V
IN
– V
DD
)
DC/DC Controller
Output-Voltage Adjust Range
(V
OUT
)
Reference
0°C
≤
T
J
≤
85°C (±1.0%)
−40°C ≤
T
J
≤
125°C (±1.5%)
Load Regulation
Line Regulation
FB Bias Current
Enable Control
EN Logic Level High
EN Logic Level Low
EN Bias Current
Oscillator
Switching Frequency
(6)
Maximum Duty Cycle
Minimum Duty Cycle
Minimum Off-Time
(7)
Condition
Min.
4.5
Typ.
Max.
28
Units
V
µA
µA
V
V
mV
mV
V
FB
= 1.5V (non-switching)
V
EN
= 0V
V
IN
= 7V to 28V, I
DD
= 25mA
V
DD
Rising
I
DD
= 25mA
4.8
3.7
450
5
5
4.2
400
380
750
10
5.4
4.5
600
0.8
5.5
V
0.792
0.788
0.8
0.8
0.25
0.25
50
0.808
0.812
V
%
%
I
OUT
= 3A to 9A (Continuous Mode)
V
IN
= 4.5V to 28V
V
FB
= 0.8V
1.8
500
nA
V
0.6
V
EN
= 12V
450
V
FB
= 0V
V
FB
= 1.0V
6
600
82
0
300
30
750
V
µA
kHz
%
%
ns
July 2011
4
M9999-071311-A
Micrel, Inc.
MIC26903
Electrical Characteristics
(5)
(Continued)
PV
IN
= V
IN
= V
EN
= 12V, V
BST
– V
SW
= 5V; T
A
= 25°C, unless noted.
Bold
values indicate
−40°C
≤
T
J
≤
+125°C.
Parameter
Soft-Start
Soft-Start time
Short-Circuit Protection
Current-Limit Threshold
Current-Limit Threshold
Short-Circuit Current
Internal FETs
Top-MOSFET R
DS (ON)
Bottom-MOSFET R
DS (ON)
SW Leakage Current
V
IN
Leakage Current
Power Good (PG)
PG Threshold Voltage
PG Hysteresis
PG Delay Time
PG Low Voltage
Thermal Protection
Over-Temperature Shutdown
Over-Temperature Shutdown
Hysteresis
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
3. The device is not guaranteed to function outside operating range.
4. PD
(MAX)
= (T
J(MAX)
– T
A
)/
θ
JA
, where
θ
JA
depends upon the printed circuit layout. A 5 square inch 4 layer, 0.62”, FR-4 PCB with 2oz finish copper weight
per layer is used for the
θ
JA
.
5. Specification for packaged product only.
6. Measured in test mode.
7. The maximum duty-cycle is limited by the fixed mandatory off-time t
OFF
of typically 300ns.
Condition
Min.
Typ.
5
Max.
Units
ms
V
FB
= 0.8V, T
J
= 25°C
V
FB
= 0.8V, T
J
= 125°C
V
FB
= 0V
I
SW
= 3A
I
SW
= 3A
V
EN
= 0V
V
EN
= 0V
Sweep V
FB
from Low to High
Sweep V
FB
from High to Low
Sweep V
FB
from Low to High
Sweep V
FB
<
0.9
×
V
NOM
, I
PG
= 1mA
T
J
Rising
12.5
11.25
15
15
4
27
10.5
20
20
A
A
A
mΩ
mΩ
60
25
85
92
5.5
100
70
160
15
200
95
µA
µA
%V
OUT
%V
OUT
µs
mV
°C
°C
July 2011
5
M9999-071311-A
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