Selectable positive or negative edge synchronization
Synchronous output enable
Output frequency: 15MHz to 100MHz
CMOS outputs
3 skew grades:
IDT59920A-2: t
SKEW0
<250ps
IDT59920A-5: t
SKEW0
<500ps
IDT59920A-7: t
SKEW0
<750ps
3-level inputs for PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA I
OL
high drive outputs
Low Jitter: <200ps peak-to-peak
Outputs drive 50Ω terminated lines
Ω
Pin-compatible with Cypress CY7B9920
Available in SOIC package
The IDT59920A is a high fanout phase lock loop clock driver in-
tended for high performance computing and data-communications appli-
cations. The IDT59920A has CMOS outputs.
The IDT59920A maintains Cypress CY7B9920 compatibility while
providing two additional features: Synchronous Output Enable (GND/
sOE),
and Positive/Negative Edge Synchronization (V
DDQ
/PE). When
the GND/sOE pin is held low, all outputs are synchronously enabled
(CY7B9920 compatibility). However, if GND/sOE is held high, all out-
puts except Q2 and Q3 are synchronously disabled.
Furthermore, when the V
DDQ
/PE is held high, all outputs are synchro-
nized with the positive edge of the REF clock input (CY7B9920 compat-
ibility). When V
DDQ
/PE is held low, all outputs are synchronized with the
negative edge of REF.
The FB signal is compared with the input REF signal at the phase
detector in order to drive the VCO. Phase differences cause the VCO of
the PLL to adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
V
DDQ
/PE
G ND/sOE
Q
0
Q
1
Q
2
Q
3
PLL
REF
Q
4
Q
5
FS
Q
6
Q
7
FB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2001
Integrated Device Technology, Inc.
SEPTEMBER 2001
DSC 5846/2
IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
I
T
STG
Description
Supply Voltage to Ground
DC Input Voltage
Maximum Power Dissipation (T
A
= 85°C)
Storage Temperature
Max
–0.5 to +7
–0.5 to +7
530
–65 to +150
Unit
V
V
mW
°C
REF
V
DDQ
FS
NC
V
DDQ
/PE
V
DDN
Q
0
Q
1
GND
Q
2
Q
3
V
DDN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
TEST
NC
GND/sOE
V
DDN
Q
7
Q
6
GND
Q
5
Q
4
V
DDN
FB
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
C
IN
Description
Input Capacitance
Typ.
5
Max.
7
Unit
pF
SOIC
TOP VIEW
NOTE:
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not
production tested.
PIN DESCRIPTION
Pin Name
REF
FB
TEST
(1)
GND/
sOE
(1)
V
DDQ
/PE
FS
(2)
Type
IN
IN
IN
IN
IN
IN
Description
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q
2
and Q
3
) in a LOW state - Q
2
and Q
3
may be used as the
feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
Frequency range select. 3 level input.
FS = GND: 15 to 35MHz
FS = MID (or open): 25 to 60MHz
FS = V
DD
: 40 to 100MHz
Q
0
- Q
7
V
DDN
V
DDQ
GND
OUT
PWR
PWR
PWR
Eight clock output
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
NOTES:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.
2. This input is wired to V
DD
, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional
lock time before all data sheet limits are achieved.
2
IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
IDT59920A-5, -7
(Industrial)
Symbol
V
DD
T
A
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
4.5
-40
Max.
5.5
+85
IDT59920A-2
(Commercial)
Min.
4.75
0
Max.
5.25
+70
Unit
V
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
(1)
Input MID Voltage
(1)
Input LOW Voltage
(1)
Input Leakage Current
(REF, FB Inputs Only)
I
3
I
PU
I
PD
V
OH
V
OL
I
OS
3-Level Input DC Current (TEST, FS)
Input Pull-Up Current (V
DDQ
/PE)
Input Pull-Down Current (GND/sOE)
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
(2)
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
DD
or GND
V
DD
= Max.
V
IN
= V
DD
V
IN
= V
DD
/2
V
IN
= GND
V
DD
= Max., V
IN
= GND
V
DD
= Max., V
IN
= V
DD
V
DD
= Min., I
OH
=
−
16mA
V
DD
= Min., I
OH
=
−
40mA
V
DD
= Max., V
O
= GND
V
DD
= Min., I
OL
= 46mA
HIGH Level
MID Level
LOW Level
—
—
—
—
—
—
V
DD
−
0.75
—
—
±200
±50
±200
±100
±100
—
—
0.45
N/A
V
mA
µA
µA
V
µA
Min.
V
DD
−
1.35
—
V
DD
/2
−
0.5
—
—
V
DD
−
1
Max.
—
1.35
—
V
DD
/2+0.5
1
±5
Unit
V
V
V
V
V
µA
NOTES:
1. These inputs are normally wired to V
DD
, GND, or unconnected. Internal termination resistors bias unconnected inputs to V
DD
/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional t
LOCK
time before all datasheet limits are achieved.
2. Outputs are not to be shorted.
POWER SUPPLY CHARACTERISTICS
Symbol
I
DDQ
∆I
DD
I
DDD
I
TOT
Parameter
Quiescent Power Supply Current
Power Supply Current per Input HIGH
Dynamic Power Supply Current per Output
Total Power Supply Current
Test Conditions
(1)
V
DD
= Max., TEST = MID, REF = LOW,
GND/sOE = LOW, All outputs unloaded
V
DD
= Max., V
IN
= 3.4V
V
DD
= Max., C
L
= 0pF
V
DD
= 5V, F
REF
= 25MHz, C
L
= 240pF
(1)
V
DD
= 5V, F
REF
= 33MHz, C
L
= 240pF
(1)
V
DD
= 5V, F
REF
= 66MHz, C
L
= 240pF
(1)
NOTE:
1. For eight outputs, each loaded with 30pF.
Typ.
10
0.4
100
53
63
117
Max.
40
1.5
160
—
—
—
Unit
mA
mA
µA/MHz
mA
3
IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
t
PWC
D
H
R
EF
Description
(1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Reference Clock Input
Min.
—
3
10
15
Max.
10
—
90
100
Unit
ns/V
ns
%
MHz
NOTE:
1. Where pulse width implied by D
H
is less than t
PWC
limit, t
PWC
limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT59920A-2
Symbol
F
REF
t
RPWH
t
RPWL
t
SKEW0
t
DEV
t
PD
t
ODCV
t
ORISE
t
OFALL
t
LOCK
t
JR
Parameter
FS = LOW
REF Frequency Range
REF Pulse Width HIGH
(1,8)
REF Pulse Width LOW
(1,8)
Zero Output Skew (All Outputs)
(1,3,4)
Device-to-Device Skew
(1,2,5)
REF Input to FB Propagation Delay
(1,7)
Output Duty Cycle Variation from 50%
(1)
Output Rise Time
(1)
Output Fall Time
(1)
PLL Lock Time
(1,6)
Cycle-to-Cycle Output Jitter
(1)
RMS
Peak-to-Peak
FS = MED
FS = HIGH
Min.
15
25
40
3
3
—
—
Typ.
—
—
—
—
—
0.1
—
0
0
2
2
—
—
—
Max.
35
60
100
—
—
0.25
0.75
0.25
0.5
2.5
2.5
0.5
25
200
Min.
15
25
40
3
3
—
—
IDT59920A-5
Typ.
—
—
—
—
—
0.25
—
0
0
2
2
—
—
—
Max.
35
60
100
—
—
0.5
1.25
0.5
1.2
3.5
3.5
0.5
25
200
Min.
15
25
40
3
3
—
—
IDT59920A-7
Typ.
—
—
—
—
—
0.3
—
0
0
3
3
—
—
—
Max.
35
60
100
—
—
0.75
1.65
0.7
1.5
5
5
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
MHz
Unit
−
0.25
−
0.5
0.5
0.5
—
—
—
−
0.5
−
1.2
0.5
0.5
—
—
—
−
0.7
−
1.5
0.5
0.5
—
—
—
NOTES:
1. All timing and jitter tolerances apply for F
NOM
> 25MHz. Guaranteed by design and characterization, not subject to production testing.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. t
SKEW
is the skew between all outlets. See AC TEST LOADS.
4. For IDT59920A-2 t
SKEW0
is measured with C
L
= 0pF; for C
L
= 30pF, t
SKEW0
= 0.45ns Max.
5. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
DD
, ambient temperature, air flow, etc.)
6. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
DD
is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
7. t
PD
is measured with REF input rise and fall times (from 0.2V
DD
to 0.8V
DD
) of 1.5ns.
8. Refer to INPUT TIMING REQUIREMENTS for more detail.
4
IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TEST LOADS AND WAVEFORMS
V
DD
V
D D
80%
Vth = 0.5V
DD
≤
1.5ns
≤
1.5ns
100
Ω
Outpu t
20%
0V
100
Ω
C
L
CMOS Input Test Waveform
C
L
= 50pF (C
L
= 30pF for -2 and -5 de vice s)
Test Load
t
O R ISE
t
OF AL L
0.8 V
DD
0.2 V
DD
CMOS Output Waveform
AC TIMING DIAGRAM
t
R EF
t
R PW H
REF
t
RP W L
t
PD
t
OD CV
t
O D CV
FB
t
JR
Q
t
S K E W
t
SK E W
OTHER Q
NOTES:
Skew:
t
SKEW
:
t
DEV
:
t
ODCV
:
t
LOCK
:
The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5) and terminated with V
DD
/2.
The skew between all outputs.
The output-to-output skew between any two devices operating under the same conditions (V
DD
, ambient temperature, air flow, etc.)
The deviation of the output from a 50% duty cycle.
The time that is required before synchronization is achieved. This specification is valid only after V
DD
is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until t
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