Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizer
FEATURES
•
Complete 1.3 GHz single chip system
•
Four PNP band switch buffers (40 mA)
•
33 V output tuning voltage
•
In-lock detector
•
15-bit programmable divider
•
Programmable reference divider ratio
(512, 640 or 1024)
•
Programmable charge-pump current (60 or 280
µA)
•
Varicap drive disable
•
Universal bus protocol I
2
C-bus or 3-wire bus (the
TSA5520/TSA5521 I
2
C-bus mode only includes the
write mode; if both read and write modes are required
the TSA5526/TSA5527 devices should be selected):
– bus protocol for 18 or 19 bits transmission
(3-wire bus)
– extra protocol for 27 bits for test and features
(3-wire bus)
– address plus 4 data bytes transmission (I
2
C-bus)
– three independent I
2
C-bus addresses
•
Low power and low radiation.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TSA5520M
TSA5520T
TSA5521M
TSA5521T
SSOP16
SO16
SSOP16
SO16
DESCRIPTION
APPLICATIONS
TSA5520; TSA5521
•
TV tuners and front ends
•
VCR tuners.
VERSION
SOT369-1
SOT109-1
SOT369-1
SOT109-1
plastic shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 16 leads; body width 3.9 mm
1996 Oct 10
2
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizer
QUICK REFERENCE DATA
SYMBOL
V
CC1
V
CC2
I
CC1
I
CC2
f
RF
V
i(RF)
PARAMETER
supply voltage (+5 V)
band switch supply voltage (12 V)
supply current
band switch supply current
RF input frequency
RF input voltage
80 to 150 MHz
150 MHz to 1 GHz
1 to 1.3 GHz
f
xtal
I
o(PNP)
P
tot
T
stg
T
amb
Notes
1. One band switch buffer ON with 40 mA.
2. One buffer ON, I
o
= 40 mA; two buffers ON, maximum sum of I
o
= 50 mA.
3. The power dissipation is calculated as follows:
P
D
=
V
CC1
×
I
CC1
+
V
CC2
× (
I
CC2
–
I
o
)
+
I
o
×
V
CE
(
satPNP
)
+
(
V33
⁄
2
) ⁄
27 kΩ
2
TSA5520; TSA5521
CONDITIONS
MIN.
4.5
V
CC1
−
TYP.
−
12
20
50
−
−
−
−
4.0
−
250
−
−
MAX.
5.5
13.5
25
55
1300
+3
+3
+3
4.48
50
400
+150
+85
UNIT
V
V
mA
mA
MHz
dBm
dBm
dBm
MHz
mA
mW
°C
°C
note 1
−
64
−25
−28
−15
3.2
4
−
−40
−20
crystal oscillator input frequency
PNP band switch buffers output current note 2
total power dissipation
IC storage temperature
operating ambient temperature
note 3
1996 Oct 10
3
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizer
GENERAL DESCRIPTION
The device is a single-chip PLL frequency synthesizer
designed for TV and VCR tuning systems. The circuit
consists of a divide-by-eight prescaler with its own
preamplifier, a 15-bit programmable divider, a crystal
oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge-pump
which drives the tuning amplifier and the 33 V output.
Four high-current PNP band switch buffers are provided
for band switching. Two PNP buffers can be switched on
simultaneously. The sum of the collector currents is limited
to 50 mA.
Depending on the reference divider ratio (512, 640 or
1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz using a 4 MHz crystal.
The lock detector output is LOW when the PLL loop is
locked. In the test mode, this output is used as a test
output for f
ref
and 1/2f
div
(see Table 6). The device can be
controlled in accordance with the I
2
C-bus format or the
3-wire bus format depending on the voltage applied to the
SW input (see Table 2).
I
2
C-bus format (SW = LOW)
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the four PNP band switch buffers, set the charge-pump
current and the reference divider ratio.
Table 1
Differences between TSA5520 and TSA5521
DATA WORD
18-bit
19-bit
18-bit or 19-bit
TSA5520; TSA5521
The device has three independent I
2
C-bus addresses
which can be selected by applying a specific voltage on the
CE input (see Table 5). The general address C2 is always
valid. When the I
2
C-bus format is fully used, TSA5520 and
TSA5521 are equal.
3-wire bus format (SW = V
CC1
or open-circuit)
Data is transmitted to the device during a HIGH level on
the CE input (enable line pin 15). The device is compatible
with 18-bit and 19-bit data formats. The first four bits are
used to program the PNP band switch buffers and the
remaining bits are used to control the programmable
divider. A 27-bit data format may also be used to set the
charge-pump current, the reference divider ratio and for
test purposes. The difference between TSA5520 and
TSA5521 are given in Table 1.
When the 27-bit format is used, the TSA5520 and
TSA5521 are equal and the reference divider is controlled
by the RSA and RSB bits (see Table 7). More details are
given in Chapter “Functional description” Section “3-wire
bus mode (SW = open-circuit or V
CC1
); see
Figs 3, 4 and 5”.
TYPE NUMBER
TSA5520
TSA5520
TSA5521
Notes
REFERENCE DIVIDER
512
(1)
1024
(1)
640
(2)
FREQUENCY STEP (kHz)
62.5
31.25
50
1. The selection of the reference divider is given by an automatic identification of the data word length.
2. The reference divider is set to 640 at power-on reset.
1996 Oct 10
4
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