r
r
TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
TAOS091D − DECEMBER 2008
D
Approximates Human Eye Response
D
Approximately 4
y
More Sensitive Than
TSL2560/61 Device
PACKAGE CS
6-LEAD CHIPSCALE
(TOP VIEW)
D
Programmable Interrupt Function with
D
D
D
D
D
D
User-Defined Upper and Lower Threshold
Settings
16-Bit Digital Output with SMBus (TSL2568)
at 100 kHz or I
2
C (TSL2569) Fast-Mode at
400 kHz
Programmable Analog Gain and Integration
Time Supporting 1,000,000-to-1 Dynamic
Range
Available in Ultra-Small 1.25 mm
y
1.75 mm
Chipscale Package
Automatically Rejects 50/60-Hz Lighting
Ripple
Low Active Power (0.75 mW Typical) with
Power Down Mode
RoHS Compliant
V
DD
1
ADDR SEL 2
GND 3
6 SDA
5 INT
4 SCL
Package Drawings are Not to Scale
PACKAGE T
6-LEAD TMB
(TOP VIEW)
V
DD
1
ADDR SEL 2
GND 3
6 SDA
5 INT
4 SCL
Description
The TSL2568 and TSL2569 are high-sensitivity light-to-digital converters that transform light intensity to a digital
signal output capable of direct I
2
C (TSL2569) or SMBus (TSL2568) interface. Each device combines one
broadband photodiode (visible plus infrared) and one infrared-responding photodiode on a single CMOS
integrated circuit capable of providing a near-photopic response over an effective 20-bit dynamic range (16-bit
resolution). Two integrating ADCs convert the photodiode currents to a digital output that represents the
irradiance measured on each channel. This digital output can be input to a microprocessor where illuminance
(ambient light level) in lux is derived using an empirical formula to approximate the human eye response. The
TSL2568 device permits an SMB-Alert style interrupt, and the TSL2569 device supports a traditional level style
interrupt that remains asserted until the firmware clears it.
While useful for general purpose light sensing applications, the TSL2568/69 devices are designed particularly
for display panels (LCD, OLED, etc.) with the purpose of extending battery life and providing optimum viewing
in diverse lighting conditions. Display panel backlighting, which can account for up to 30 to 40 percent of total
platform power, can be automatically managed. Both devices are also ideal for controlling keyboard illumination
based upon ambient lighting conditions. Illuminance information can further be used to manage exposure
control in digital cameras. The TSL2568/69 devices are ideal in notebook/tablet PCs, LCD monitors, flat-panel
televisions, cell phones, and digital cameras. In addition, other applications include street light control, security
lighting, sunlight harvesting, machine vision, and automotive instrumentation clusters.
The
LUMENOLOGY
r
Company
Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road
S
Suite 300
S
Plano, TX 75074
S
(972) 673-0759
r
www.taosinc.com
1
r
Copyright
E
2008, TAOS Inc.
TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
TAOS091D − DECEMBER 2008
Functional Block Diagram
Channel 0
Visible and IR
Integrating
A/D Converter
V
DD
= 2.7 V to 3.5 V
Channel 1
IR Only
ADDR SEL
Address Select
Command
Register
ADC
Register
Interrupt
INT
SCL
Two-Wire Serial Interface
SDA
Detailed Description
The TSL2568 and TSL2569 are second-generation ambient light sensor devices. Each contains two integrating
analog-to-digital converters (ADC) that integrate currents from two photodiodes. Integration of both channels
occurs simultaneously. Upon completion of the conversion cycle, the conversion result is transferred to the
Channel 0 and Channel 1 data registers, respectively. The transfers are double-buffered to ensure that the
integrity of the data is maintained. After the transfer, the device automatically begins the next integration cycle.
Communication to the device is accomplished through a standard, two-wire SMBus or I
2
C serial bus.
Consequently, the TSL256x device can be easily connected to a microcontroller or embedded controller. No
external circuitry is required for signal conditioning, thereby saving PCB real estate as well. Since the output
of the TSL256x device is digital, the output is effectively immune to noise when compared to an analog signal.
The TSL256x devices also support an interrupt feature that simplifies and improves system efficiency by
eliminating the need to poll a sensor for a light intensity value. The primary purpose of the interrupt function is
to detect a meaningful change in light intensity. The concept of a
meaningful change
can be defined by the user
both in terms of light intensity and time, or persistence, of that change in intensity. The TSL256x devices have
the ability to define a threshold above and below the current light level. An interrupt is generated when the value
of a conversion exceeds either of these limits.
Copyright
E
2008, TAOS Inc.
r
r
The
LUMENOLOGY
r
Company
2
www.taosinc.com
TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
TAOS091D − DECEMBER 2008
Terminal Functions
TERMINAL
NAME
ADDR SEL
GND
INT
SCL
SDA
V
DD
T PKG
NO.
2
3
5
4
6
1
O
I
I/O
TYPE
I
SMBus device select — three-state
Power supply ground. All voltages are referenced to GND.
Level or SMB Alert interrupt — open drain.
SMBus serial clock input terminal — clock signal for SMBus serial data.
SMBus serial data I/O terminal — serial data I/O for SMBus.
Supply voltage.
DESCRIPTION
Available Options
DEVICE
TSL2568
TSL2568
TSL2569
TSL2569
INTERFACE
SMBus
SMBus
I
2
C
I
2
C
PACKAGE − LEADS
Chipscale
TMB-6
Chipscale
TMB-6
PACKAGE DESIGNATOR
CS
T
CS
T
ORDERING NUMBER
TSL2568CS
TSL2568T
TSL2569CS
TSL2569T
Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
DD
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 V
Digital output voltage range, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.8 V
Digital output current, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1 mA to 20 mA
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
Recommended Operating Conditions
MIN
Supply voltage, V
DD
Operating free-air temperature, T
A
SCL, SDA input low voltage, V
IL
SCL, SDA input high voltage, V
IH
2.7
−30
−0.5
2.1
NOM
3
MAX
3.6
70
0.8
3.6
UNIT
V
°C
V
V
Electrical Characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
Active
I
DD
V
OL
I
LEAK
Supply current
INT, SDA output low voltage
Leakage current
Power down
3 mA sink current
0
−5
TEST CONDITIONS
MIN
TYP
0.24
3.2
MAX
0.6
15
0.4
5
UNIT
mA
μA
V
μA
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Copyright
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2008, TAOS Inc.
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TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
TAOS091D − DECEMBER 2008
Operating Characteristics, High Gain (16), V
DD
= 3 V, T
A
= 255C, (unless otherwise noted) (see
Notes 2, 3, 4, 5)
TSL2568T, TSL2569T
PARAMETER
f
osc
Oscillator frequency
Ch0
Dark ADC count value
E
e
= 0 T
int
= 402 ms
0,
T
int
> 178 ms
Full scale ADC count
value (Note 6)
T
int
= 101 ms
T
int
= 13.7 ms
13 7
λ
p
= 640 nm, T
int
= 101 ms
E
e
= 33
μW/cm
2
λ
p
= 940 nm, T
int
= 101 ms
E
e
= 106
μW/cm
2
ADC count value
λ
p
= 640 nm, T
int
= 101 ms
E
e
= 34.5
μW/cm
2
λ
p
= 940 nm, T
int
= 101 ms
E
e
= 110.9
μW/cm
2
ADC count value ratio:
t l
ti
Ch1/Ch0
λ
p
= 640 nm T
int
= 101 ms
nm,
λ
p
= 940 nm T
int
= 101 ms
nm,
λ
p
= 640 nm T
int
= 101 ms
nm,
R
e
Irradiance responsivity
λ
p
= 940 nm T
int
= 101 ms
nm,
Fluorescent light source:
T
int
= 402 ms
R
v
Illuminance responsivity
Incandescent light source:
T
int
= 402 ms
ADC count value ratio:
Ch1/Ch0
Fluorescent light source:
T
int
= 402 ms
Incandescent light source:
T
int
= 402 ms
Fluorescent light source:
T
int
= 402 ms
Incandescent light source:
T
int
= 402 ms
Fluorescent light source:
T
int
= 402 ms
Incandescent light source:
T
int
= 402 ms
Ch0
Ch1
Ch0
Ch1
0.65
0.60
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
Ch1
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
0.18
0 18
0.73
0 73
0.25
0 25
0.88
0 88
121
30.3
37.7
33.2
185
35
599
330
0.19
0.55
0 55
11.6
2.2
37.5
20.7
1
1
1.35
1.40
0.65
0.60
0.32
0 32
1.03
1 03
0.14
0 14
0.70
0 70
2800
2800
3000
4000
1000
4000
3520
3000
4000
840
4000
3440
0.21
0 21
0.86
0 86
116
24
36
31
180
33.3
537
307
0.19
0.57
0 57
11.1
2.1
33.8
19.3
1
1
1.35
1.40
counts/
lux
counts/
lux
counts/
(μW/
cm
2
)
0.28
0 28
1.01
1 01
5200
counts
5000
5200
counts
TEST CONDITIONS
CHANNEL
MIN
690
0
0
TYP
735
MAX
780
8
8
65535
65535
37177
37177
5047
5047
5000
TSL2568CS, TSL2569CS
MIN
690
0
0
TYP
735
MAX
780
8
8
65535
65535
37177
37177
5047
5047
counts
counts
UNIT
kHz
R
v
Illuminance responsivity,
low gain mode (Note 7)
(Sensor Lux) /
(actual Lux) high gain
Lux),
mode (Note 8)
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2008, TAOS Inc.
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TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
TAOS091D − DECEMBER 2008
NOTES: 2. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible 640 nm LEDs
and infrared 940 nm LEDs are used for final product testing for compatibility with high-volume production.
3. The 640 nm irradiance E
e
is supplied by an AlInGaP light-emitting diode with the following characteristics: peak wavelength
λp
= 640 nm and spectral halfwidth
Δλ½
= 17 nm.
4. The 940 nm irradiance E
e
is supplied by a GaAs light-emitting diode with the following characteristics: peak wavelength
λp
= 940 nm and spectral halfwidth
Δλ½
= 40 nm.
5. Integration time T
int
, is dependent on internal oscillator frequency (f
osc
) and on the integration field value in the timing register as
described in the
Register Set
section. For nominal f
osc
= 735 kHz, nominal T
int
= (number of clock cycles)/f
osc
.
Field value 00: T
int
= (11
×
918)/f
osc
= 13.7 ms
Field value 01: T
int
= (81
×
918)/f
osc
= 101 ms
Field value 10: T
int
= (322
×
918)/f
osc
= 402 ms
Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01),
and 322/322 = 1 (field value 10).
6. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also
by a 2-count offset.
Full scale ADC count value = ((number of clock cycles)/2 − 2)
Field value 00: Full scale ADC count value = ((11
×
918)/2 − 2) = 5047
Field value 01: Full scale ADC count value = ((81
×
918)/2 − 2) = 37177
Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit register. This full scale ADC count value is reached
for 131074 clock cycles, which occurs for T
int
= 178 ms for nominal f
osc
= 735 kHz.
7. Low gain mode has 16
y
lower gain than high gain mode: (1/16 = 0.0625).
8. The sensor Lux is calculated using the empirical formula shown on p. 22 of this data sheet based on measured Ch0 and Ch1 ADC
count values for the light source specified. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual
Lux) ratio is estimated based on the variation of the 640 nm and 940 nm optical parameters. Devices are not 100% tested with
fluorescent or incandescent light sources.
AC Electrical Characteristics, V
DD
= 3 V, T
A
= 255C (unless otherwise noted)
PARAMETER
†
t
(CONV)
f
(SCL)
t
(BUF)
t
(HDSTA)
t
(SUSTA)
t
(SUSTO)
t
(HDDAT)
t
(SUDAT)
t
(LOW)
t
(HIGH)
t
(TIMEOUT)
t
F
t
R
C
i
†
TEST CONDITIONS
MIN
12
0
10
1.3
0.6
0.6
0.6
0
100
1.3
0.6
25
TYP
100
MAX
400
400
100
UNIT
ms
kHz
kHz
μs
μs
μs
μs
μs
ns
μs
μs
Conversion time
Clock frequency (I
2
C only)
Clock frequency (SMBus only)
Bus free time between start and stop condition
Hold time after (repeated) start condition. After
this period, the first clock is generated.
Repeated start condition setup time
Stop condition setup time
Data hold time
Data setup time
SCL clock low period
SCL clock high period
Detect clock/data low timeout (SMBus only)
Clock/data fall time
Clock/data rise time
Input pin capacitance
0.9
35
300
300
10
ms
ns
ns
pF
Specified by design and characterization; not production tested.
The
LUMENOLOGY
r
Company
r
r
www.taosinc.com
Copyright
E
2008, TAOS Inc.
5
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