74LVCH322244A
32-bit buffer/line driver; 30
series termination resistors; 5 V
tolerant input/output; 3-state
Rev. 3 — 16 December 2011
Product data sheet
1. General description
The 74LVCH322244A is a 32-bit non-inverting buffer/line driver with 3-state outputs. The
3-state outputs are controlled by the output enable inputs nOE. A HIGH on input nOE
causes the outputs to assume a high-impedance OFF-state.
The device is designed with 30
series termination resistors in both HIGH and LOW
output stages to reduce line noise.
To ensure the high-impedance state during power-up or power-down, input nOE should
be tied to V
CC
through a pull-up resistor; the minimum value of the resistor is determined
by the current-sinking capability of the driver.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. These features allow the use of these devices in a mixed 3.3 V and 5 V
environment.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
or floating data inputs at a valid logic level.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground
bounce
Direct interface with TTL levels
Integrated 30
termination resistors
All data inputs have bus hold
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVCH322244A
32-bit buffer/line driver; 30
resistors; 5 V tolerance; 3-state
Packaged in plastic fine-pitch ball grid array package
3. Ordering information
Table 1:
Ordering information
Package
Temperature
range
Name
Description
plastic low profile fine pitch ball grid array package;
96 balls; body 13.5
5.5
1.05 mm
Version
SOT536-1
Type number
74LVCH322244AEC
40 C
to +85
C
LFBGA96
4. Functional diagram
A5
A6
B5
B6
A3
1A0
1A1
1A2
1A3
1OE
1Y0
1Y1
1Y2
1Y3
A2
A1
B2
B1
E5
E6
F5
F6
H4
3A0
3A1
3A2
3A3
3OE
3Y0
3Y1
3Y2
3Y3
E2
E1
F2
F1
J5
J6
K5
K6
J3
5A0
5A1
5A2
5A3
5OE
5Y0
5Y1
5Y2
5Y3
J2
J1
K2
K1
N5
N6
P5
P6
T4
7A0
7A1
7A2
7A3
7OE
7Y0
7Y1
7Y2
7Y3
N2
N1
P2
P1
C5
C6
D5
D6
A4
2A0
2A1
2A2
2A3
2OE
2Y0
2Y1
2Y2
2Y3
C2
C1
D2
D1
G5
G6
H6
H5
H3
4A0
4A1
4A2
4A3
4OE
4Y0
4Y1
4Y2
4Y3
G2
G1
H1
H2
L5
L6
M5
M6
J4
6A0
6A1
6A2
6A3
6OE
6Y0
6Y1
6Y2
6Y3
L2
L1
M2
M1
R5
R6
T6
T5
T3
8A0
8A1
8A2
8A3
8OE
8Y0
8Y1
8Y2
8Y3
R2
R1
T1
T2
mna472
Fig 1. Logic symbol
V
CC
data
input
to internal circuit
mna473
Fig 2. Bushold circuit
74LVCH322244A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
2 of 14
NXP Semiconductors
74LVCH322244A
32-bit buffer/line driver; 30
resistors; 5 V tolerance; 3-state
5. Pinning information
5.1 Pinning
mna471
6
5
4
3
2
1
1A1
1A0
1A3
1A2
2A1
2A0
2A3
2A2
3A1
3A0
3A3
3A2
4A1
4A0
4A2
4A3
5A1
5A0
5A3
5A2
6A1
6A0
6A3
6A2
7A1
7A0
7A3
7A2
8A1
8A0
8A2
8A3
2OE GND VCC GND GND VCC GND 3OE 6OE GND VCC GND GND VCC GND 7OE
1OE GND VCC GND GND VCC GND 4OE 5OE GND VCC GND GND VCC GND 8OE
1Y0
1Y1
A
1Y2
1Y3
B
2Y0
2Y1
C
2Y2
2Y3
D
3Y0
3Y1
E
3Y2
3Y3
F
4Y0
4Y1
G
4Y3
4Y2
H
5Y0
5Y1
J
5Y2
5Y3
K
6Y0
6Y1
L
6Y2
6Y3
M
7Y0
7Y1
N
7Y2
7Y3
P
8Y0
8Y1
R
8Y3
8Y2
T
Fig 3. Pin configuration
5.2 Pin description
Table 2:
Ball
nOE (n = 1 to 8)
1A[0:3]
2A[0:3]
3A[0:3]
4A[0:3]
5A[0:3]
6A[0:3]
7A[0:3]
8A[0:3]
1Y[0:3]
2Y[0:3]
3Y[0:3]
4Y[0:3]
5Y[0:3]
6Y[0:3]
7Y[0:3]
8Y[0:3]
V
CC
GND
Pin description
Symbol
A3, A4, H4, H3, J3 J4, T4, T3
A5, A6, B5, B6
C5, C6, D5, D6
E5, E6, F5, F6
G5, G6, H6, H5
J5, J6, K5, K6
L5, L6, M5, M6
N5, N6, P5, P6
R5, R6, T6, T5
A2, A1, B2, B1
C2, C1, D2, D1
E2, E1, F2, F1
G2, G1, H1, H2
J2, J1, K2, K1
L2, L1, M2, M1
N2, N1, P2, P1
R2, R1, T1, T2
C3, C4, F3, F4, L3, L4, P3, P4
B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, M3,
M4, N3, N4, R3, R4
supply voltage
ground (0 V)
data output
Description
3-state output enable inputs (active LOW)
data input
74LVCH322244A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
3 of 14
NXP Semiconductors
74LVCH322244A
32-bit buffer/line driver; 30
resistors; 5 V tolerance; 3-state
6. Functional description
Table 3:
Input
nOE
L
L
H
[1]
Functional table
[1]
Output
nAn
L
H
X
nYn
L
H
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
200
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0
output HIGH or LOW state
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
200
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
Above 70
C
the value of P
tot
derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and fall rate
output HIGH or LOW state
output 3-state
in free air
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
Conditions
Min
1.65
1.2
0
0
0
40
-
-
Typ
-
-
-
-
-
-
-
-
Max
3.6
-
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
V
C
ns/V
ns/V
74LVCH322244A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
4 of 14
NXP Semiconductors
74LVCH322244A
32-bit buffer/line driver; 30
resistors; 5 V tolerance; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level input V
CC
= 1.2 V
voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
2
mA; V
CC
= 1.65 V
I
O
=
4
mA; V
CC
= 2.3 V
I
O
=
6
mA; V
CC
= 2.7 V
I
O
=
12
mA; V
CC
= 3.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 2 mA; V
CC
= 1.65 V
I
O
= 4 mA; V
CC
= 2.3 V
I
O
= 6 mA; V
CC
= 2.7 V
I
O
= 12 mA; V
CC
= 3.0 V
I
I
I
OZ
I
OFF
I
CC
I
CC
input leakage
current
OFF-state
output current
power-off
leakage supply
supply current
additional
supply current
input
capacitance
bus hold LOW
current
V
CC
= 3.6 V;
V
I
= 5.5 V or GND
V
I
= V
IH
or V
IL
; V
CC
= 3.6
V; V
O
= 5.5 V or GND;
V
CC
= 0 V; V
I
or V
O
= 5.5 V
V
CC
= 3.6 V;
V
I
= V
CC
or GND; I
O
= 0 A
per input pin;
V
CC
= 2.7 V to 3.6 V;
V
I
= V
CC
0.6 V; I
O
= 0 A
V
CC
= 0 V to 3.6 V;
V
I
= GND to V
CC
V
CC
= 1.65 V; V
I
= 0.58 V
V
CC
= 2.3 V; V
I
= 0.7 V
V
CC
= 3.0 V; V
I
= 0.8 V
[3][4]
[2]
40 C
to +85
C
Min
1.08
0.65
V
CC
1.7
2.0
-
-
-
-
V
CC
0.2
1.2
1.8
2.2
2.2
-
-
-
-
-
-
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
V
CC
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.1
5
Max
-
-
-
-
0.12
0.35
V
CC
0.7
0.8
-
-
-
-
-
0.2
0.45
0.6
0.4
0.55
5
5
10
40
500
40 C
to +125
C
Min
1.08
0.65
V
CC
1.7
2.0
-
-
-
-
V
CC
0.3
1.05
1.65
2.05
2.0
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.12
0.7
0.8
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
20
20
20
160
5000
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
A
A
A
0.35
V
CC
V
[2]
C
I
I
BHL
-
10
30
75
5.0
-
-
-
-
-
-
-
-
10
25
60
-
-
-
-
pF
A
A
A
74LVCH322244A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2011
5 of 14
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