CY7C1243KV18, CY7C1245KV18
36-Mbit QDR
®
II+ SRAM Four-Word Burst
Architecture (2.0 Cycle Read Latency)
36-Mbit QDR
®
II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
Features
■
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1243KV18 – 2 M × 18
CY7C1245KV18 – 1 M × 36
Separate independent read and write data ports
❐
Supports concurrent transactions
450 MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 900 MHz) at 450 MHz
Available in 2.0 clock cycle latency
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR
®
II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in × 18, and × 36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8 V ± 0.1 V; I/O V
DDQ
= 1.4 V to
❐
Supports both 1.5 V and 1.8 V I/O supply
V
DD[1]
■
■
■
■
■
Functional Description
The CY7C1243KV18, and CY7C1245KV18 are 1.8 V
synchronous pipelined SRAMs, equipped with QDR II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common I/O devices. Each port is accessed through
a common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with four 18-bit words
(CY7C1243KV18), or 36-bit words (CY7C1245KV18) that burst
sequentially into or out of the device. Because data is transferred
into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
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HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
Selection Guide
Description
Maximum operating frequency
Maximum operating current
× 18
× 36
450 MHz
450
720
1020
400 MHz
400
660
920
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
DDQ
= 1.4 V to V
DD
.
Cypress Semiconductor Corporation
Document Number: 001-57832 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 25, 2012
CY7C1243KV18, CY7C1245KV18
Logic Block Diagram – CY7C1243KV18
D
[17:0]
18
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
19
A
(18:0)
512K x 18 Array
512K x 18 Array
512K x 18 Array
512K x 18 Array
K
K
CLK
Gen.
Control
Logic
RPS
DOFF
Read Data Reg.
CQ
72
V
REF
WPS
BWS
[1:0]
36
Control
Logic
36
Reg.
Reg.
Reg. 18
18
18
18
CQ
18
Q
[17:0]
QVLD
Logic Block Diagram – CY7C1245KV18
D
[35:0]
36
Read Add. Decode
Write Add. Decode
A
(17:0)
18
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
18
A
(17:0)
256K x 36 Array
256K x 36 Array
256K x 36 Array
256K x 36 Array
K
K
CLK
Gen.
Control
Logic
RPS
DOFF
Read Data Reg.
CQ
144
V
REF
WPS
BWS
[3:0]
72
Control
Logic
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q
[35:0]
QVLD
Document Number: 001-57832 Rev. *E
Page 2 of 30
CY7C1243KV18, CY7C1245KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ............................................... 10
Write Cycle Descriptions ............................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port ....................................................... 12
Performing a TAP Reset ........................................... 12
TAP Registers ........................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Electrical Characteristics ...................................... 15
TAP AC Switching Characteristics ............................... 16
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Power Up Sequence in QDR II+ SRAM ......................... 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 23
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Read/Write/Deselect Sequence ................................ 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC Solutions ......................................................... 30
Document Number: 001-57832 Rev. *E
Page 3 of 30
CY7C1243KV18, CY7C1245KV18
Pin Configurations
The pin configurations for CY7C1243KV18, and CY7C1245KV18 follow.
[2]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1243KV18 (2 M × 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
CY7C1245KV18 (1 M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
NC/144M
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
NC/288M NC/72M
Note
2. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-57832 Rev. *E
Page 4 of 30
CY7C1243KV18, CY7C1245KV18
Pin Definitions
Pin Name
D
[x:0]
I/O
Pin Description
Input-
Data input signals.
Sampled on the rising edge of K and K clocks when valid write operations are active.
synchronous CY7C1243KV18
D
[17:0]
CY7C1245KV18
D
[35:0]
Input-
Write port select
active LOW.
Sampled on the rising edge of the K clock. When asserted active, a
synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
[x:0]
.
Input-
Byte write select 0, 1, 2 and 3
active LOW.
Sampled on the rising edge of the K and K clocks when
synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1243KV18
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1245KV18
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
,
BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device.
Input-
Address inputs.
Sampled on the rising edge of the K clock during active read and write operations.
synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2 M × 18 (4 arrays each of 512 K × 18) for CY7C1243KV18 and 1 M × 36 (4 arrays each
of 256 K × 36) for CY7C1245KV18. Therefore, only 19 address inputs are needed to access the entire
memory array of CY7C1243KV18 and 18 address inputs for CY7C1245KV18. These inputs are ignored
when the appropriate port is deselected.
Outputs-
Data output signals.
These pins drive out the requested data when the read operation is active. Valid
synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q
[x:0]
are automatically tri-stated.
CY7C1243KV18
Q
[17:0]
CY7C1245KV18
Q
[35:0]
Input-
Read port select
active LOW.
Sampled on the rising edge of positive input clock (K). When active, a
synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tri-stated following the next rising edge
of the K clock. Each read access consists of a burst of four sequential transfers.
Valid output
Valid output indicator.
The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
Input clock
Input clock
Echo clock
Echo clock
Input
Positive input clock input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
. All accesses are initiated on the rising edge of K.
Negative input clock input.
K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
[x:0]
.
Synchronous echo clock outputs.
This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the
Switching Characteristics on page 24.
Synchronous echo clock outputs.
This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the
Switching Characteristics on page 24.
Output impedance matching input.
This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
PLL turn off
active LOW.
Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull-up through a 10 K or less pull-up resistor. The device behaves in QDR I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to
167 MHz with QDR I timing.
TDO pin for JTAG.
Page 5 of 30
WPS
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
A
Q
[x:0]
RPS
QVLD
K
K
CQ
CQ
ZQ
DOFF
Input
TDO
Output
Document Number: 001-57832 Rev. *E
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