TN1A60
Sensitive Triac
Symbol
○
3.T2
V
DRM
= 600V
I
T(RMS)
= 1A
TO-92
▼
▲
○
2.Gate
I
TSM
=
10A
1.T1
○
1
2
3
Features
Repetitive Peak Off-State Voltage :
600V
◆
R.M.S On-State Current ( I
T(RMS)
= 1 A )
◆
High Commutation dv/dt
◆
General Description
This device is suit able for low power AC switching application, phase control application such a s fan
speed and temperature modulation control, lighting control and static switching relay where high sensi-
tivity is required in all four quadrants.
This device may substitute for Z0107MA.
Absolute Maximum Ratings
Symbol
V
DRM
I
T(RMS)
I
TSM
I
2
t
P
GM
P
G(AV)
I
GM
T
J
T
STG
Parameter
( Tj = 25°C unless otherwise specified )
Condition
Sine wave, 50 to 60 Hz
T
j
=
110
°C,
Full Sine Wave
One Cycle, 50Hz/60Hz, Peak,
Non-Repetitive
t
p = 10ms
Ratings
600
1.0
10
0.41
1
0.1
1
-
40 ~ 125
-
40 ~ 150
°C
°C
Units
V
A
A
A2s
W
W
A
Repetitive Peak Off-State Voltage
R.M.S On-State Current
Surge On-State Current
I
2
t for Fusing
Peak Gate Power Dissipation
Average Gate Power Dissipation
Peak Gate Current
Operating Junction Temperature
Storage Temperature
May.,
2010. Rev.1
copyright @ Apollo Electron Co., Ltd. All rights reserved.
1/5
TN1A60
Electrical Characteristics
(Tj =25°C unless otherwise specified)
Ratings
Symbol
Items
Repetitive Peak Off-State
Current
Peak On-State Voltage
Conditions
Min.
I
DRM
V
TM
I
+GT1
I
-GT1
I
-
GT3
Unit
Typ.
-
-
-
-
Max.
0.5
1.6
mA
V
V
D
= V
DRM
, Single Phase, Half Wave
-
I
TM
= 1 A,
tp=
380㎲
I
II
Gate Trigger Current
III
IV
I
Gate Trigger Voltage
III
IV
Non-Trigger Gate Voltage
Critical Rate of Rise Off-State
Voltage
Holding Current
V
D
=1/2 V
DRM
T
j
= 110 °C
V
D
=2/3 V
DRM
V
D
=12V, I
T
=0.1A
V
D
=
12V,
R
L
=100
Ω
V
D
=
12V,
R
L
=100
Ω
10
10
mA
10
-
30
1.8
-
-
-
-
-
-
-
I
+GT3
V
+GT1
V
-GT1
V
-GT3
V
+GT3
V
GD
dv/dt
I
H
-
-
1.8
1.8
2.0
V
-
-
-
-
0.1
5
-
-
-
-
-
25
V
V
/㎲
mA
2/5
TN1A60
Fig 1. Gate Characteristics
10
1
Fig 2. On-State Voltage
10
1
V
GM
(6V)
25
℃
10
0
P
G(AV)
(0.1W)
On-State Current [A]
Gate Voltage [V]
P
GM
(1W)
T
J
= 125 C
10
0
o
25
℃
I
I
I
+
GT1
_
GT1
_
GT3
I
+
GT3
I
GM
(1A)
T
J
= 25 C
o
V
GD
(0.2V)
10
-1
10
0
10
1
10
2
10
3
10
-1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Gate Current [mA]
On-State Voltage [V]
Fig 3. On State Current vs.
Maximum Power Dissipation
θ
= 180
o
θ
= 150
o
θ
= 120
o
θ
= 90
θ
= 60
θ
= 30
0.6
o
o
o
Fig 4. On State Current vs.
Allowable Case Temperature
Allowable Case Temperature [
o
C]
130
120
110
100
90
80
70
60
50
40
0.0
1.5
Power Dissipation [W]
1.2
π
θ
360°
θ
2
π
0.9
θ
: Conduction Angle
π
θ
360°
θ
2
π
0.3
θ
: Conduction Angle
0.2
0.4
0.6
0.8
θ
θ
θ
θ
θ
θ
1.0
= 30
o
= 60
o
= 90
o
= 120
o
= 150
o
= 180
1.2
o
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
RMS On-State Current [A]
RMS On-State Current [A]
Fig 5. Surge On-State Current Rating
( Non-Repetitive )
12
10
Fig 6. Gate Trigger Voltage vs.
Junction Temperature
10
Surge On-State Current [A]
V
+
GT1
_
GT1
+
GT3
_
GT3
8
60Hz
V
GT
(25 C)
V
GT
(t C)
o
o
V
V
1
6
V
4
50Hz
2
0.1
-50
0
0
10
Time (cycles)
10
1
10
2
0
50
100
o
150
Junction Temperature [ C]
3/5
TN1A60
Fig 7. Gate Trigger Current vs.
Junction Temperature
10
10
3
Fig 8. Transient Thermal Impedance
Transient Thermal Impedance [ C/W]
R
θ
(J-A)
10
2
I
I
GT
(25
o
C)
I
GT
(t
o
C)
I
1
I
+
GT1
_
GT1
_
GT3
o
R
θ
(J-C)
10
1
I
0.1
-50
+
GT3
0
50
100
o
150
10
0
10
-2
10
-1
10
0
10
1
10
2
10
3
Junction Temperature [ C]
Time (sec)
4/5
TN1A60
TO-92 Package Dimension
Dim.
A
B
C
D
E
F
G
H
I
J
mm
Min.
Typ.
4.2
3.7
4.43
14.07
4.83
14.87
0.4
4.43
4.83
0.45
2.54
2.54
0.33
0.48
0.013
0.174
0.174
0.554
Max.
Min.
Inch
Typ.
0.165
0.146
0.190
0.585
0.016
0.190
0.017
0.100
0.100
0.019
Max.
A
E
B
F
C
G
1
D
2
3
1. T1
2. Gate
3. T2
J
H
I
5/5
FPGA/CPLD
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