VERY LOW POWER 1.8V
16K/8K/4K X 16 DUAL-PORT
STATIC RAM
Features
◆
◆
IDT70P269/259/249L
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
Both ports configurable to standard SRAM or time-
multiplexed address/data interface
High-speed access
– Industrial: 65ns (max.), ADM mode
– Industrial: 40ns (max.), Standard SRAM mode
Low-power operation
IDT70P269/259/249L
Active: 27mW (typ.)
Standby: 3.6
µ
W (typ.)
Supports 3.0V, 2.5V and 1.8V I/O's
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
Power supply isolation functionality to aid system power
management
Separate upper-byte and lower-byte control
Input Read Register
Output Drive Register
BUSY
and Interrupt Flag
On-chip port arbitration logic
Fully asynchronous operation from either port
Available in 100 Ball 0.5mm-pitch BGA
Industrial temperature range (-40°C to +85°C)
Green parts available, see ordering information
Functional Block Diagram
IRR1 – IRR0
(2)
SFEN#
IRR/ODR
ODR4 – ODR0
I/O
15L
– I/O
8L
Data <15..0>
I/O
7L
– I/O
0L
Mux’ed
Address /
Data
I/O Control
Memory Array
16K/8K/4K x 16
AddrR <13..0>
AddrR <13..0>
Mux’ed
Address /
Data
I/O Control
Data <15..0>
I/O
15R
– I/O
8R
I/O
7R
– I/O
0R
ADV
L
UB
L
LB
L
ADV
R
UB
R
LB
R
A
13L
– A
0L
A
13R
– A
0R
MSEL
L
Address
Decode
Address
Decode
MSEL
R
CS
L
OE
L
WE
L
BUSY
L
INT
L
Control Logic
CS
R
OE
R
WE
R
BUSY
R
INT
R
7146 drw 01
NOTES:
1. A
13
- A
0
for IDT70P269; A
12
- A
0
for IDT70P259; A
11
- A
0
for IDT70P249.
2. IRR0 and IRR1 are not available for IDT70P269.
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc.
DSC-7146/1
IDT70P269/259/249L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Description
The IDT70P269/259/249 is a very low power 16K/8K/4K x 16 Dual-
Port Static RAM. The IDT70P269/259/249 is designed to be used as a
stand-alone 256/128/64K-bit Dual-Port SRAM.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CS
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 27mW of power.
The IDT70P269/259/249 is packaged in a 100 ball 0.5mm- pitch Ball
Grid Array. The package is a 1mm thick and designed to fit in wireless
handset applications.
Pin Configurations
(2,3)
70P269/259/249BY
BYG-100
100-Ball 0.5mm Pitch BGA
Top View
1
A
B
C
D
E
F
G
H
J
K
A
5R
2
A
8R
3
A
11R
4
UB
R
5
V
SS
6
ADV
R
7
I/O
15R
8
I/O
12R
9
I/O
10R
10
V
SS
A
B
C
D
E
F
G
H
J
K
A
3R
A
4R
A
7R
A
9R
CS
R
WE
R
OE
R
V
DDIOR
I/O
9R
I/O
6R
A
0R
A
1R
A
2R
A
6R
LB
R
IRR
1 (1)
I/O
14R
I/O
11R
I/O
7R
V
SS
ODR
4
ODR
2
BUSY
R
INT
R
A
10R
A
12R (3)
I/O
13R
I/O
8R
I/O
5R
I/O
2R
V
SS
DNU
ODR
3
INT
L
V
SS
V
SS
I/O
4R
V
DDIOR
I/O
1R
V
SS
SFEN
ODR
1
BUSY
L
A
1L
V
DD
V
SS
I/O
3R
I/O
0R
I/O
15L
V
DDIOL
ODR
0
A
2L
A
5L
A
12L(3)
OE
L
I/O
3L
I/O
11L
I/O
12L
I/O
14L
I/O
13L
A
0L
A
4L
A
9L
LB
L
CS
L
I/O
1L
V
DDIOL
MSEL
R
MSEL
L
I/O
10L
A
3L
A
7L
A
10L
IRR
0 (2)
V
DD
V
SS
I/O
4L
I/O
6L
I/O
8L
I/O
9L
A
6L
A
8L
A
11L
UB
L
ADV
L
WE
L
I/O
0L
I/O
2L
I/O
5L
I/O
7L
1
2
3
4
5
6
7
8
9
10
7146 drw 02
NOTES:-
1. This pin is A
13R
for IDT70P269.
2. This pin is A
13L
for IDT70P269.
3. This pin is DNU for IDT70P249.
4. DNU pins are "do not use". No trace or power component can be connected to these pins.
6.42
2
OCTOBER 16, 2008
IDT70P269/259/249L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Pin Names
Left Port
CS
L
WE
L
OE
L
A
0L
- A
13L
MSEL
L
(2)
I/O
0L
- I/O
15L
ADV
L
(3)
UB
L
LB
L
INT
L
BUSY
L
(1)
Right Port
CS
R
WE
R
OE
R
A
0R
- A
13R
MSEL
R
(2)
I/O
0R
- I/O
15R
ADV
R
UB
R
LB
R
INT
R
BUSY
R
SFEN
(3)
(1)
Description
Chip Select (Input)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
Mode Select (Input)
Address/Data (Input/Output)
Address Latch Enable (Input)
Upper Byte Enable (Input)
Lower Byte Enable (Input)
Interrupt Flag (Output)
Busy Flag (Output)
Special Function Enable (Input)
Input Read Register (Inputs)
Output Drive Register (Outputs)
Core Power Supply (Input)
Ground (Input)
Left Port Power Supply (Input)
Right Port Power Supply (Input)
7146 tbl 01
NOTES:
1. A
13
- A
0
for IDT70P269; A
12
- A
0
for IDT70P259; A
11
- A
0
for IDT70P249.
2. MSEL = 0 for Standard SRAM operation, MSEL = 1 for Address/Data Mux
(ADM) operation.
3. ADV is only used when the port is in ADM mode.
4. IRR
0
is A
13L
and IRR
1
is A
13R
for 70P269.
IRR
0
- IRR
1
(4)
ODR
0
- ODR
4
VDD
VSS
VDDIO
L
VDDIO
R
Truth Table I: ADM Interface Read/Write Control
Inputs
ADV
X
X
X
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
CS
H
X
X
L
L
L
L
L
L
WE
X
X
X
H
H
H
L
L
L
OE
X
H
X
L
L
L
X
X
X
UB
X
X
H
L
H
L
L
H
L
LB
X
X
H
L
L
H
L
L
H
Outputs
I/O
0 -
I/O
15
High-Z
High-Z
High-Z
DATA
OUT
(I/O
0
- I/O
15
)
DATA
OUT
(I/O
0
- I/O
7
)
High-Z (I/O
8
- I/O
15
)
High-Z (I/O
0
- I/O
7
)
DATA
OUT
(I/O
8
- I/O
15
)
DATA
IN
(I/O
0
- I/O
15
)
DATA
IN
(I/O
0
- I/O
7
)
High-Z (I/O
8
- I/O
15
)
High-Z (I/O
0
- I/O
7
)
DATA
IN
(I/O
8
- I/O
15
)
Mode
Deselected/Power Down
Output Disable
Upper and Lower Bytes Deselected
Read Upper and Lower Bytes
Read Lower Byte Only
Read Upper Byte Only
Write Upper and Lower Bytes
Write Lower Byte Only
Write Upper Byte Only
7146 tbl 02a
6.42
3
OCTOBER 16, 2008
IDT70P269/259/249L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Truth Table II: Standard SRAM Interface Read/Write Control
Inputs
CS
H
X
X
L
L
L
L
L
L
WE
X
X
X
H
H
H
L
L
L
OE
X
H
X
L
L
L
X
X
X
UB
X
X
H
L
H
L
L
H
L
LB
X
X
H
L
L
H
L
L
H
Outputs
I/O
0 -
I/O
15
High-Z
High-Z
High-Z
DATA
OUT
(I/O
0
- I/O
15
)
DATA
OUT
(I/O
0
- I/O
7
)
High-Z (I/O
8
- I/O
15
)
High-Z (I/O
0
- I/O
7
)
DATA
OUT
(I/O
8
- I/O
15
)
DATA
IN
(I/O
0
- I/O
15
)
DATA
IN
(I/O
0
- I/O
7
)
High-Z (I/O
8
- I/O
15
)
High-Z (I/O
0
- I/O
7
)
DATA
IN
(I/O
8
- I/O
15
)
Mode
Deselected/Power Down
Output Disable
Upper and Lower Bytes Deselected
Read Upper and Lower Bytes
Read Lower Byte Only
Read Upper Byte Only
Write Upper and Lower Bytes
Write Lower Byte Only
Write Upper Byte Only
7146 tbl 02b
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
T
BIAS
(3)
T
STG
T
JN
I
OUT
Rating
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Junction Temperature
DC Output Current
Commercial
& Industrial
-0.5 to V
DDIOX
+0.5
-55 to +125
-65 to +150
+150
20
Unit
V
o
C
C
C
o
o
mA
7146 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DDIOX
+ 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited
to < 20mA for the period over V
TERM
= V
DDIOX
+ 0.5V
.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
6.42
4
OCTOBER 16, 2008
IDT70P269/259/249L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Capacitance
Symbol
C
IN
C
OUT
(TA = +25°C, f = 1.0MHz)
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
7146 tbl 05
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Ambient
Temperature
-40
O
C to +85
O
C
GND
V
DD
1.8V
+
100mV
2.5V
+
100mV
3.0V
+
300mV
7146 tb l 04
Industrial
0V
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
NOTE :
1. This is the parameter T
A
. This is the "instant on" case temperature.
DC Electrical Characteristics Over the Operating and
Temperature and Supply Voltage Range
(V
DD
= 1.8V)
70P269/259/249
Ind'l Only
Symbol
Parameter
Output High Voltage (I
0
H
= -100
µA)
Output High Voltage (I
0
H
= -2 mA)
V
OH
Output High Voltage (I
0
H
= -2 mA)
Output Low Voltage (I
0
L
= 100
µA)
Output Low Voltage (I
0
L
= 2 mA)
V
OL
Output Low Voltage (I
0
L
= 2 mA)
P1 I/O
Voltage
P2 I/O
Voltage
Min.
V
DDIO
- 0.2
2.0
2.1
___
Typ.
___
Max.
___
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1.8V (any port)
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
___
___
___
___
___
0.2
0.4
0.4
0.2
0.2
0.2
V
DDIO
+ 0.2
V
DDIO
+ 0.3
V
DDIO
+ 0.2
0.4
0.6
0.7
1
1
1
1
1
1
1
1
1
___
___
___
___
___
___
___
___
V
OL
ODR
ODR Output Low Voltage (I
0
L
= 8 mA)
3.0V (any port)
1.8V (any port)
2.5V (any port)
___
___
1.2
1.7
2.0
-0.2
-0.3
-0.2
-1
-1
-1
-1
-1
-1
-1
-1
-1
___
___
V
IH
Input High Voltage
3.0V (any port)
1.8V (any port)
2.5V (any port)
___
___
___
V
IL
Input Low Voltage
3.0V (any port)
1.8V
2.5V
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
___
___
___
I
OZ
Output Leakage Current
3.0V
1.8V
2.5V
___
µA
___
___
I
CEX
ODR
ODR Output Leakage Current
V
OUT
= V
DDIO
3.0V
1.8V
2.5V
___
µA
___
___
I
IX
Input Leakage Current
3.0V
___
µA
7146 tbl 06
6.42
5
OCTOBER 16, 2008
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
