MIC24054
12V, 9A High-Efficiency Buck Regulator
SuperSwitcher II
General Description
Features
•
Hyper Light Load efficiency – up to 80% at 10mA
The Micrel MIC24054 is a constant-frequency,
synchronous DC/DC buck regulator featuring adaptive on-
•
Hyper Speed Control architecture enables
time control architecture. The MIC24054 operates over a
−
High delta V operation (V
IN
= 19V and V
OUT
= 0.8V)
supply range of 4.5V to 19V. It has an internal linear
−
Small output capacitance
regulator which provides a regulated 5V to power the
•
Input voltage range: 4.5V to 19V
internal control circuitry. The MIC24054 operates at a
constant 600kHz switching frequency in continuous
•
Output current up to 9A
conduction mode and can be used to provide up to 9A of
•
Up to 95% efficiency
output current. The output voltage is adjustable down to
•
Adjustable output voltage from 0.8V to 5.5V
0.8V.
•
±1% FB accuracy
®
Micrel’s Hyper Light Load architecture provides the same
•
Any Capacitor stable
−
zero-to-high ESR
high-efficiency and ultra-fast transient response as the
•
600kHz switching frequency
Hyper Speed Control architecture under medium to heavy
loads, but also maintains high efficiency under light load
•
Power good (PG) output
conditions by transitioning to variable frequency,
•
Foldback current-limit and “hiccup” mode short-circuit
discontinuous mode operation.
protection
The MIC24054 offers a full suite of protection features to
•
Safe start-up into pre-biased loads
ensure protection of the IC during fault conditions. These
•
–40°C to +125°C junction temperature range
include undervoltage lockout to ensure proper operation
•
Available in 28-pin 5mm
×
6mm QFN package
under power-sag conditions, thermal shutdown, internal
soft-start to reduce the inrush current, foldback current
Applications
limit and “hiccup mode” short-circuit protection. The
MIC24054 includes a power good (PG) output to allow
•
Servers and work stations
simple sequencing.
•
Routers, switches, and telecom equipment
The 9A Hyper Speed Control part, MIC24053, is also
•
Base stations
available on Micrel’s web site.
All support documentation can be found on Micrel’s web
site at:
www.micrel.com.
___________________________________________________________________________________________________________
Typical Application
Efficiency (VIN = 12V)
vs. Output Current
100
95
90
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
0.8V
EFFICIENCY (%)
85
80
75
70
65
60
55
50
0
2
4
6
8
10
VIN = 12V
12
OUTPUT CURRENT (A)
Hyper Light Load is a registered trademark of Micrel, Inc.
Hyper Speed Control, SuperSwitcher II, and Any Capacitor are trademarks of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
October 2012
M9999-102512-A
Micrel, Inc.
MIC24054
Ordering Information
Part Number
MIC24054YJL
Switching Frequency
600kHz
Voltage
Adjustable
Package
28-Pin 5mm
×
6mm QFN
Junction Temperature
Range
–40°C to +125°C
Lead Finish
Pb-Free
Pin Configuration
28-Pin 5mm x 6mm QFN (JL)
(Top View)
Pin Description
Pin Number
1
Pin Name
PVDD
Pin Function
5V Internal Linear Regulator output. PVDD supply is the power MOSFET gate drive supply voltage
and created by internal LDO from V
IN
. When VIN < +5.5V, PVDD should be tied to PVIN pins. A
2.2µF ceramic capacitor from the PVDD pin to PGND (Pin 2) must be placed next to the IC.
Power Ground. PGND is the ground path for the MIC24054 buck converter power stage. The
PGND pins connect to the low-side N-Channel internal MOSFET gate drive supply ground, the
sources of the MOSFETs, the negative terminals of input capacitors, and the negative terminals of
output capacitors. The loop for the power ground should be as small as possible and separate
from the signal ground (SGND) loop.
No Connect.
Switch Node output. Internal connection for the high-side MOSFET source and low-side MOSFET
drain. Due to the high speed switching on this pin, the SW pin should be routed away from
sensitive nodes.
High-Side N-internal MOSFET Drain Connection input. The PVIN operating voltage range is from
4.5V to 19V. Input capacitors between the PVIN pins and the power ground (PGND) are required
and keep the connection short.
Boost output. Bootstrapped voltage to the high-side N-channel MOSFET driver. A Schottky diode is
connected between the PVDD pin and the BST pin. A boost capacitor of 0.1μF is connected
between the BST pin and the SW pin. Adding a small resistor at the BST pin can slow down the
turn-on time of high-side N-Channel MOSFETs.
2, 5, 6, 7, 8, 21
PGND
3
4, 9, 10, 11, 12
13,14,15,
16,17,18,19
NC
SW
PVIN
20
BST
October 2012
2
M9999-102512-A
Micrel, Inc.
MIC24054
Pin Description (Continued)
Pin Number
Pin Name
Pin Function
Current Sense input. The CS pin senses current by monitoring the voltage across the low-side
MOSFET during the OFF-time. The current sensing is necessary for short circuit protection and zero
current cross comparator. In order to sense the current accurately, connect the low-side MOSFET
drain to SW using a Kelvin connection. The CS pin is also the high-side MOSFET’s output driver
return.
Signal Ground. SGND must be connected directly to the ground planes. Do not route the SGND pin
to the PGND pad on the top layer, see PCB layout guidelines for details.
Feedback input. Input to the transconductance amplifier of the control loop. The FB pin is regulated
to 0.8V. A resistor divider connecting the feedback to the output is used to adjust the desired output
voltage.
Power Good output. Open drain output. The PG pin is externally tied with a resistor to VDD. A high
output is asserted when V
OUT
>
92% of nominal.
Enable input. A logic level control of the output. The EN pin is CMOS-compatible. Logic high =
enable, logic low = shutdown. In the off state, supply current of the device is greatly reduced (typically
5µA). The EN pin should not be left floating.
Power Supply Voltage input. Requires bypass capacitor to SGND.
5V Internal Linear Regulator output. VDD supply is the supply bus for the IC control circuit. VDD is
created by internal LDO from VIN. When VIN
< +5.5V,
VDD should be tied to PVIN pins. A 1µF
ceramic capacitor from the VDD pin to SGND pins must be place next to the IC.
22
CS
23
24
25
26
27
28
SGND
FB
PG
EN
VIN
VDD
October 2012
3
M9999-102512-A
Micrel, Inc.
MIC24054
Absolute Maximum Ratings
(1)
PVIN to PGND...............................................
−0.3V
to +29V
VIN to PGND .................................................
−0.3V
to PVIN
PVDD, VDD to PGND .....................................
−0.3V
to +6V
V
SW
, V
CS
to PGND .............................
−0.3V
to (PVIN +0.3V)
V
BST
to V
SW
........................................................
−0.3V
to 6V
V
BST
to PGND ..................................................
−0.3V
to 35V
V
FB
, V
PG
to PGND .............................
−0.3V
to (VDD + 0.3V)
V
EN
to PGND .......................................
−0.3V
to (VIN +0.3V)
PGND to SGND............................................
−0.3V
to +0.3V
Junction Temperature .............................................. +150°C
Storage Temperature (T
S
) .........................
−65°C
to +150°C
Lead Temperature (soldering, 10s) ............................ 260°C
(2).
ESD Rating ................................................ ESD Sensitive
Operating Ratings
(3)
Supply Voltage (PVIN, VIN) .............................. 4.5V to 19V
PVDD, VDD Supply Voltage (PVDD, VDD) ..... 4.5V to 5.5V
Enable Input (V
EN
) .................................................. 0V to V
IN
Junction Temperature (T
J
) ........................
−40°C
to +125°C
Maximum Power Dissipation ...................................... Note 4
(4)
Package Thermal Resistance
5mm x 6mm QFN-28 (θ
JA
) ................................ 28°C/W
Electrical Characteristics
(5)
PVIN = VIN = V
EN
= 12V, V
BST
– V
SW
= 5V; T
A
= 25°C, unless noted.
Bold
values indicate
−40°C
≤ T
J
≤ +125°C.
Parameter
Power Supply Input
Input Voltage Range (VIN, PVIN)
Quiescent Supply Current
Shutdown Supply Current
VDD Supply Voltage
VDD Output Voltage
VDD UVLO Threshold
VDD UVLO Hysteresis
Dropout Voltage (VIN – VDD)
DC/DC Controller
Output-Voltage Adjust Range (V
OUT
)
Reference
Feedback Reference Voltage
Load Regulation
Line Regulation
FB Bias Current
Notes:
1.
2.
3.
4.
5.
Exceeding the absolute maximum rating may damage the device.
Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
The device is not guaranteed to function outside operating range.
PD
(MAX)
= (T
J(MAX)
– T
A
)/
θ
JA
, where
θ
JA
depends upon the printed circuit layout. A 5 square inch 4 layer, 0.62”, FR-4 PCB with 2oz finish copper
weight per layer is used for the
θ
JA
.
Specification for packaged product only.
Condition
Min.
4.5
Typ.
Max.
19
Units
V
µA
µA
V
V
mV
mV
V
V
FB
= 1.5V (non-switching)
V
EN
= 0V
VIN = 7V to 19V, I
DD
= 25mA
VDD Rising
I
DD
= 25mA
0.8
0°C
≤
T
J
≤
85°C (±1.0%)
−40°C ≤
T
J
≤
125°C (±1.5%)
I
OUT
= 3A to 9A (Continuous Mode)
VIN = 4.5V to 19V
V
FB
= 0.8V
0.792
0.788
4.8
3.7
450
5
5
4.2
400
380
750
10
5.4
4.5
600
5.5
0.8
0.8
0.25
0.25
50
0.808
0.812
V
%
%
500
nA
October 2012
4
M9999-102512-A
Micrel, Inc.
MIC24054
Electrical Characteristics
(5)
(Continued)
PVIN = VIN = V
EN
= 12V, V
BST
– V
SW
= 5V; T
A
= 25°C, unless noted.
Bold
values indicate
−40°C
≤ T
J
≤ +125°C.
Parameter
Condition
Min.
Typ.
Enable Control
EN Logic Level High
EN Logic Level Low
EN Bias Current
Oscillator
Switching Frequency
Minimum Duty Cycle
Minimum Off-Time
Soft-Start
Soft-Start time
Short-Circuit Protection
Peak Inductor Current-Limit Threshold
Short-Circuit Current
Internal FETs
Top-MOSFET R
DS (ON)
Bottom-MOSFET R
DS (ON)
SW Leakage Current
V
IN
Leakage Current
Power Good (PG)
PG Threshold Voltage
PG Hysteresis
PG Delay Time
PG Low Voltage
Thermal Protection
Over-Temperature Shutdown
Over-Temperature Shutdown Hysteresis
Notes:
6.
7.
Measured in test mode.
The maximum duty-cycle is limited by the fixed mandatory off-time t
OFF
of typically 300ns.
(6)
(7)
Max.
Units
V
1.8
0.6
V
EN
= 12V
V
OUT
= 2.5V
V
FB
= 0V
V
FB
= 1.0V
450
6
600
82
0
300
3
V
FB
= 0.8V, T
J
= 25°C
V
FB
= 0.8V, T
J
= 125°C
V
FB
= 0V
I
SW
= 3A
I
SW
= 3A
V
EN
= 0V
V
EN
= 0V
Sweep V
FB
from Low to High
Sweep V
FB
from High to Low
Sweep V
FB
from Low to High
Sweep V
FB
<
0.9
×
V
NOM
, I
PG
= 1mA
T
J
Rising
85
92
5.5
100
70
160
15
200
12.5
11.25
30
750
V
µA
kHz
%
%
ns
ms
Maximum Duty Cycle
14
8
27
10.5
20
A
A
mΩ
mΩ
60
25
95
µA
µA
%V
OUT
%V
OUT
µs
mV
°C
°C
October 2012
5
M9999-102512-A
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