Datasheet
Serial EEPROM Series Standard EEPROM
I
2
C BUS EEPROM (2-Wire)
BR24G08-3
General Description
BR24G08-3 is an 8Kbit serial EEPROM of I
2
C BUS interface.
Features
Completely conforming to the world standard I
2
C
BUS.
All controls available by 2 ports of serial clock
(SCL) and serial data (SDA)
Other devices than EEPROM can be connected to
the same port, saving microcontroller port
1.6V to 5.5V Single Power Source Operation most
suitable for battery use
1.6V to 5.5V wide limit of operating voltage, possible
FAST MODE 400KHz operation
Up to 16Byte in Page Write Mode
Bit Format 1K x 8
Self-timed Programming Cycle
Low Current Consumption
Prevention of Write Mistake
Write (Write Protect) Function Added
Prevention of Write Mistake at Low Voltage
More than 1 million write cycles
More than 40 years data retention
Noise Filter Built in SCL / SDA Terminal
Initial delivery state FFh
Packages
W (Typ) x D(Typ) x H(Max)
DIP-T8
9.30mm x 6.50mm x 7.10mm
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
SOP8
5.00mm x 6.20mm x 1.71mm
TSSOP-B8M
3.00mm x 6.40mm x 1.10mm
SOP- J8M
4.90mm x 6.00mm x 1.80mm
TSSOP-B8J
3.00mm x 4.90mm x 1.10mm
SOP- J8
4.90mm x 6.00mm x 1.65mm
MSOP8
2.90mm x 4.00mm x 0.90mm
SSOP-B8
3.00mm x 6.40mm x 1.35mm
VSON008X2030
2.00mm x 3.00mm x 0.60mm
Figure 1.
○Product
structure：Silicon monolithic integrated circuit
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©2013 ROHM Co., Ltd. All rights reserved.
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○This
product has not designed protection against radioactive rays
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TSZ02201-0R2R0G100190-1-2
27.Oct.2014 Rev.004
BR24G08-3
Absolute Maximum Ratings
(Ta=25℃)
Parameter
Supply Voltage
Symbol
V
CC
Rating
-0.3 to +6.5
0.45 (SOP8)
0.45 (SOP-J8M)
0.45 (SOP-J8)
0.30 (SSOP-B8)
Power Dissipation
Pd
0.33 (TSSOP-B8)
0.33 (TSSOP-B8M)
0.31 (TSSOP-B8J)
0.31 (MSOP8)
0.30 (VSON008X2030)
0.80 (DIP-T8)
Storage Temperature
Operating Temperature
Input Voltage /
Output Voltage
Junction
Temperature
Electrostatic discharge
voltage
(human body model)
Tstg
Topr
‐
Tjmax
V
ESD
-65 to +150
-40 to +85
-0.3 to V
CC
+1.0
150
-4000 to +4000
℃
℃
V
℃
V
W
Unit
V
Remark
Datasheet
Derate by 4.5mW/°C when operating above Ta=25°C
Derate by 4.5mW/°C when operating above Ta=25°C
Derate by 4.5mW/°C when operating above Ta=25°C
Derate by 3.0mW/°C when operating above Ta=25°C
Derate by 3.3mW/°C when operating above Ta=25°C
Derate by 3.3mW/°C when operating above Ta=25°C
Derate by 3.1mW/°C when operating above Ta=25°C
Derate by 3.1mW/°C when operating above Ta=25°C
Derate by 3.0mW/°C when operating above Ta=25°C
Derate by 8.0mW/°C when operating above Ta=25°C
The Max value of Input voltage/ Output voltage is not over 6.5V.
When the pulse width is 50ns or less the Min value of Input
voltage/Output voltage is not below -0.8V.
Junction temperature at the storage condition
Memory Cell Characteristics
(Ta=25℃, V
CC
=1.6V to 5.5V)
Parameter
Write Cycles
(1)
Data Retention
(1)
(1)Not 100% TESTED
Limit
Min
Typ
1,000,000
-
40
-
Max
-
-
Unit
Times
Years
Recommended Operating Ratings
Parameter
Power Source Voltage
Input Voltage
Symbol
V
CC
V
IN
Rating
1.6 to 5.5
0 to V
CC
Unit
V
DC Characteristics
(Unless otherwise specified, Ta=-40℃ to +85℃, V
CC
=1.6V to 5.5V)
Parameter
Input High Voltage1
Input Low Voltage1
Input High Voltage2
Input Low Voltage2
Output Low Voltage1
Output Low Voltage2
Input Leakage Current
Output Leakage Current
Supply Current (Write)
Supply Current (Read)
Standby Current
Symbol
V
IH1
V
IL1
V
IH2
V
IL2
V
OL1
V
OL2
I
LI
I
LO
I
CC1
I
CC2
I
SB
Limit
Min
0.7V
CC
-0.3
(2)
0.8V
CC
-0.3
(2)
-
-
-1
-1
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
Max
V
CC
+1.0
+0.3V
CC
V
CC
+1.0
0.2V
CC
0.4
0.2
1
1
2.0
0.5
2.0
Unit
V
V
V
V
V
V
µA
µA
mA
mA
µA
Conditions
1.7V≦V
CC
≦5.5V
1.7V≦V
CC
≦5.5V
1.6V≦V
CC
＜1.7V
1.6V≦V
CC
＜1.7V
I
OL
=3.0mA, 2.5V≦V
CC
≦5.5V
(SDA)
I
OL
=0.7mA, 1.6V≦V
CC
＜2.5V
(SDA)
V
IN
=0 to V
CC
V
OUT
=0 to V
CC
(SDA)
V
CC
=5.5V, f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
V
CC
=5.5V, f
SCL
=400kHz
Random read, current read, sequential read
V
CC
=5.5V, SDA・SCL=V
CC
A0,A1,A2=GND,WP=GND
(2) When the pulse width is 50ns or less, it is -0.8V.
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TSZ02201-0R2R0G100190-1-2
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BR24G08-3
AC Characteristics
(Unless otherwise specified, Ta=-40℃ to +85℃, V
CC
=1.6V to 5.5V)
Parameter
Clock Frequency
Data Clock High Period
Data Clock Low Period
SDA, SCL (INPUT) Rise Time
(1)
SDA, SCL (INPUT) Fall Time
(1)
SDA (OUTPUT) Fall Time
(1)
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time
Output Data Hold Time
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA and SCL)
WP Hold Time
WP Setup Time
WP High Period
(1) Not 100% TESTED.
Condition Input data level:V
IL
=0.2×Vcc V
IH
=0.8×Vcc
Input data timing reference level: 0.3×Vcc/0.7×Vcc
Output data timing reference level: 0.3×Vcc/0.7×Vcc
Rise/Fall time :
≦20ns
Datasheet
Symbol
f
SCL
t
HIGH
t
LOW
t
R
t
F1
t
F2
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
PD
t
DH
t
SU:STO
t
BUF
t
WR
t
I
t
HD:WP
t
SU:WP
t
HIGH:WP
Limit
Min
-
0.6
1.2
-
-
-
0.6
0.6
0
100
0.1
0.1
0.6
1.2
-
-
1.0
0.1
1.0
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
400
-
-
1.0
1.0
0.3
-
-
-
-
0.9
-
-
-
5
0.1
-
-
-
Unit
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
µs
µs
µs
µs
Serial Input / Output Timing
tR
SCL
70%
30%
70% 70%
30%
tF1
tHIGH
70%
30%
70%
30%
tHD:STA
70%
70%
30%
70%
tLOW
tSU:DAT
70%
tHD:DAT
70%
30%
DATA(1)
DATA(n)
ACK
ACK
70%
SDA
(入力)
(INPUT)
SDA
(出力)
(OUTPUT)
tBUF
tPD
70%
30%
tDH
70%
30%
30%
D1
D0
tWR
30%
30%
tF2
○
Input read at the rise edge of SCL
70%
70%
SDA
30%
30%
(output)
○
Data output in sync with the fall of SCL
tSU:WP
tSU:WP
tHD:WP
tHD:WP
STOP CONDITION
STOP CONDITION
Figure 2-(a). Serial Input / Output Timing
Figure 2-(d). WP Timing at Write Execution
70%
70%
70%
DATA(1)
DATA(1)
D1
D1
D0
D0
ACK
ACK
DATA(n)
DATA(n)
ACK
ACK
tHIGH:WP
tHIGH:WP
70%
70%
tSU:STA
70%
30%
tHD:STA
tSU:STO
tWR
tWR
30%
70%
70%
70%
Fig1-(4) Write
70%
cycle timing
START CONDITION
30%
30%
STOP CONDITION
Fig1-(5) WP timing at write execution
Fig1-(6) WP timing at write cancel
Figure 2-(b). Start-Stop Bit Timing
START CONDITION
STOP CONDITION
Figure 2-(e). WP Timing at Write Cancel
D0
write data
(n-th address)
ACK
70%
70%
tWR
STOP CONDITION
START CONDITION
Figure 2-(c). Write Cycle Timing
Fig1-(5) WP timing at write execution
Fig1-(6) WP timing at write cancel
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TSZ02201-0R2R0G100190-1-2
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BR24G08-3
Block Diagram
A0
1
8Kbit
EEPROM Array
8bit
Address
Decoder
Word
Address Register
Data
Register
Datasheet
8
VCC
A1
2
10bit
7
WP
START
STOP
A2 3
Control Circuit
ACK
6
SCL
GND 4
High Voltage
Generating circuit
Power Source
Voltage Detection
5
SDA
Figure 3. Block Diagram
Pin Configuration
(TOP VIEW)
A0
1
2
BR24G08-3
A2
3
6
5
SCL
SDA
8
VCC
A1
7
WP
GND
4
Pin Descriptions
Terminal
Name
A0
A1
A2
GND
SDA
SCL
WP
VCC
Input/
Output
-
-
Input
-
Input/
Output
Input
Input
-
Don’t use
(1)
Don’t use
(1)
Slave address setting
(2)
Reference voltage of all input / output, 0V
Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
Descriptions
(1) Pins not used as device address may be set to any of High, Low, and High-Z states
(2) A2 is not allowed to use as open.
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TSZ02201-0R2R0G100190-1-2
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BR24G08-3
Typical Performance Curves
Datasheet
6
Ta=-40℃
Ta= 25℃
Ta= 85℃
6
Ta=-40℃
Ta= 25℃
Ta= 85℃
1PIN MARK
Input High Voltage1,2: V
IH1,2
(V)
Input Low Voltage1,2: V
IL1,2
(V)
5
5
4
4
3
SPEC
2
3
2
1
1
SPEC
0
0
1
2
3
4
5
6
Supply Voltage: Vcc(v)
Figure 4. Input High Voltage1,2 vs. Supply Voltage
(A2, SCL, SDA, WP)
0
0
1
2
3
4
5
6
Supply Voltage: Vcc(v)
Figure 5. Input Low Voltage1,2 vs. Supply Voltage
(A2, SCL, SDA, WP)
1
Ta=-40℃
Ta= 25℃
Ta= 85℃
1
Ta=-40℃
Ta= 25℃
Ta= 85℃
Output Low Voltage1: V
OL1
(V)
Output Low Voltage2: V
OL2
(V)
0.8
0.8
0.6
SPEC
0.4
0.6
0.4
SPEC
0.2
0.2
0
0
1
2
3
4
5
6
0
0
1
2
3
4
5
6
Output Low Current: I
OL
(mA)
Figure 6. Output Low Voltage1 vs. Output Low Current
(V
CC
=2.5V)
Output Low Current: I
OL
(mA)
Figure 7. Output Low Voltage2 vs. Output Low Current
(V
CC
=1.6V)
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TSZ22111½15½001
5/36
TSZ02201-0R2R0G100190-1-2
27.Oct.2014 Rev.004
嵌入式系统
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