CY7C67300
EZ-Host™ Programmable Embedded
USB Host and Peripheral Controller with
Automotive AEC Grade Support
EZ-Host Features
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Single chip programmable USB dual-role (Host/Peripheral)
controller with two configurable Serial Interface Engines (SIEs)
and four USB ports
Support for USB On-The-Go (OTG) protocol
On-chip 48 MHz 16-bit processor with dynamically switchable
clock speed
Configurable IO block supporting a variety of IO options or up
to 32 bits of General Purpose IO (GPIO)
4K x 16 internal masked ROM containing built in BIOS that
supports a communication ready state with access to I
2
C™
EEPROM Interface, external ROM, UART, or USB
8K x 16 internal RAM for code and data buffering
Extended memory interface port for external SRAM and ROM
16-bit parallel Host Port Interface (HPI) with a DMA/mailbox
data path for an external processor to directly access all of the
on-chip memory and control on-chip SIEs
Fast serial port supports from 9600 baud to 2.0M baud
SPI support in both master and slave
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On-chip 16-bit DMA/mailbox data path interface
Supports 12 MHz external crystal or clock
3.3V operation
Automotive AEC grade option (–40°C to 85°C)
Package option—100-pin TQFP
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Typical Applications
EZ-Host is a very powerful and flexible dual role USB controller
that supports a wide variety of applications. It is primarily
intended to enable host capability in applications such as:
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Set top boxes
Printers
KVM switches
Kiosks
Automotive applications
Wireless access points
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CY7C67300 Block Diagram
CY7C67300
nRESET
Control
Timer 0
Timer 1
UART I/F
I2C
EEPROM I/F
Watchdog
CY16
16-bit RISC CORE
Vbus, ID
OTG
D+,D-
USB-A
HSS I/F
PWM
SPI I/F
IDE I/F
SHARED INPUT/OUTPUT PINS
GPIO [31:0]
SIE1
Host/
Peripheral
USB Ports
D+,D-
USB-B
D+,D-
USB-A
SIE2
D+,D-
USB-B
4Kx16
ROM BIOS
8Kx16
RAM
HPI I/F
GPIO
X1
X2
PLL
Mobile
Power
Booster
External MEM I/F
(SRAM/ROM)
SHARED INPUT/OUTPUT PINS
A[15:0] D[15:0]
CTRL[9:0]
Cypress Semiconductor Corporation
Document Number: 38-08015 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 11, 2013
CY7C67300
Contents
Introduction ....................................................................... 3
Functional Overview ........................................................ 3
Processor Core ........................................................... 3
Clocking ....................................................................... 3
Memory ....................................................................... 3
Interrupts ..................................................................... 3
General Timers and Watchdog Timer ......................... 3
Power Management .................................................... 3
Interface Descriptions ...................................................... 3
USB Interface .............................................................. 4
OTG Interface .............................................................. 5
External Memory Interface .......................................... 6
General Purpose IO Interface (GPIO) ......................... 8
UART Interface ............................................................ 8
I2C EEPROM Interface ............................................... 8
Serial Peripheral Interface ........................................... 8
High-Speed Serial Interface ........................................ 9
Programmable Pulse/PWM Interface .......................... 9
Host Port Interface .................................................... 10
IDE Interface ............................................................. 10
Charge Pump Interface ............................................. 11
Booster Interface ....................................................... 12
Crystal Interface ........................................................ 12
Boot Configuration Interface ...................................... 13
Operational Modes .................................................... 13
Power Savings and Reset Description ........................ 14
Power Saving Mode Description ............................... 14
Sleep ......................................................................... 14
External (Remote) Wakeup Source ........................... 15
Power-On-Reset Description ..................................... 15
Reset Pin ................................................................... 15
USB Reset ................................................................. 15
Memory Map .................................................................... 15
Mapping ..................................................................... 15
Registers ......................................................................... 17
Processor Control Registers ..................................... 17
External Memory Registers ....................................... 24
Timer Registers ......................................................... 26
General USB Registers ............................................. 28
USB Host Only Registers .......................................... 30
USB Device Only Registers ...................................... 39
OTG Control Registers .............................................. 49
GPIO Registers ......................................................... 50
IDE Registers ............................................................ 53
HSS Registers ........................................................... 56
HPI Registers ............................................................ 62
SPI Registers ............................................................ 66
UART Registers ........................................................ 74
PWM Registers ......................................................... 76
Pin Diagram ..................................................................... 80
Pin Descriptions ............................................................. 80
Absolute Maximum Ratings .......................................... 84
Operating Conditions ..................................................... 84
Crystal Requirements (XTALIN, XTALOUT) ................. 84
DC Characteristics ......................................................... 84
USB Transceiver ....................................................... 85
AC Timing Characteristics ............................................. 86
Reset Timing ........................................................... 86
Clock Timing ............................................................. 86
SRAM Read Cycle
[15]
.............................................. 87
SRAM Write Cycle
[17]
.............................................. 88
I2C EEPROM Timing-Serial IO ................................. 89
HPI (Host Port Interface) Write Cycle Timing ........... 90
HPI (Host Port Interface) Read Cycle Timing ........... 91
IDE Timing ................................................................. 92
HSS BYTE Mode Transmit ........................................ 92
HSS Block Mode Transmit ........................................ 92
HSS BYTE and BLOCK Mode Receive .................... 92
Hardware CTS/RTS Handshake ............................... 93
Register Summary .......................................................... 93
Ordering Information ...................................................... 98
Ordering Code Definitions ......................................... 98
Package Diagram ............................................................ 99
Acronyms ...................................................................... 100
Document Conventions ............................................... 100
Units of Measure ..................................................... 100
Document History Page ............................................... 101
Sales, Solutions, and Legal Information .................... 102
Worldwide Sales and Design Support ..................... 102
Products .................................................................. 102
PSoC Solutions ....................................................... 102
Document Number: 38-08015 Rev. *L
Page 2 of 112
CY7C67300
Introduction
EZ-Host™ (CY7C67300) is Cypress Semiconductor’s first
full-speed, low cost multiport host/peripheral controller. EZ-Host
is designed to easily interface to most high performance CPUs
to add USB host functionality. EZ-Host has its own 16-bit RISC
processor to act as a coprocessor or operate in standalone
mode. EZ-Host also has a programmable IO interface block
allowing a wide range of interface options.
Interrupts
EZ-Host provides 128 interrupt vectors. The first 48 vectors are
hardware interrupts and the following 80 vectors are software
interrupts.
General Timers and Watchdog Timer
EZ-Host has two built in programmable timers and a Watchdog
timer. All three timers can generate an interrupt to the EZ-Host.
Functional Overview
An overview of the processor core components are presented in
this section.
Power Management
EZ-Host has one main power saving mode, Sleep. Sleep mode
pauses all operations and provides the lowest power state.
Processor Core
EZ-Host has a general purpose 16-bit embedded RISC
processor that runs at 48 MHz.
Interface Descriptions
EZ-Host has a wide variety of interface options for connectivity.
With several interface options available, EZ-Host can act as a
seamless data transport between many different types of
devices.
See
Table 1
and
Table 2 on page 4
to understand how the inter-
faces share pins and which can coexist. Note that some inter-
faces have more then one possible port location selectable
through the GPIO control register [0xC006]. General guidelines
for interfaces are as follows:
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Clocking
EZ-Host requires a 12 MHz source for clocking. Either an
external crystal or TTL level oscillator may be used. EZ-Host has
an internal PLL that produces a 48 MHz internal clock from the
12 MHz source.
Memory
EZ-Host has a built in 4K × 16 masked ROM and an 8K × 16
internal RAM. The masked ROM contains the EZ-Host BIOS.
The internal RAM can be used for program code or data.
Table 1. Interface Options for GPIO Pins
GPIO Pins
GPIO31
GPIO30
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
HPI
IDE
PWM
HSS
HPI and IDE interfaces are mutually exclusive.
If 16-bit external memory is required, then HSS and SPI default
locations must be used.
I
2
C EEPROM and OTG do not conflict with any interfaces.
SPI
UART
I2C
SCL/SDA
SCL/SDA
OTG
OTGID
TX
RX
PWM3
INT
nRD
nWR
nCS
A1
A0
IOREADY
IOR
IOW
CS1
CS0
A2
A1
A0
D15
D14
D13
D12
D11
CTS
[1]
PWM2
PWM1
PWM0
RTS
[1]
RXD
[1]
TXD
[1]
D15
D14
D13
D12
D11
MOSI
[1]
Note
1. Default interface location.
Document Number: 38-08015 Rev. *L
Page 3 of 112
CY7C67300
Table 1. Interface Options for GPIO Pins
(continued)
GPIO Pins
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
HPI
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IDE
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PWM
HSS
SPI
SCK
[1]
nSSI
[1]
MISO
[1]
UART
I2C
OTG
Table 2. Interface Options for External Memory Bus Pins
MEM Pins
D15
D14
D13
D12
D11
D10
D9
D8
D[7:0]
A[18:0]
CONTROL
HPI
IDE
PWM
HSS
CTS
[2]
RTS
[2]
RXD
[2]
TXD
[2]
SPI
UART
I2C
OTG
MOSI
[2]
SCK
[2]
nSSI
[2]
MISO
[2]
USB Interface
EZ-Host has two built in Host/Peripheral SIEs and four USB transceivers that meet the USB 2.0 specification requirements for full and
low speed (high speed is not supported). In Host mode, EZ-Host supports four downstream ports, each support control, interrupt, bulk,
and isochronous transfers. In Peripheral mode, EZ-Host supports one peripheral port with eight endpoints for each of the two SIEs.
Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support interrupt, bulk (up
to 64 bytes/packet), or isochronous transfers (up to 1023 Bytes/packet size). EZ-Host also supports a combination of Host and
Peripheral ports simultaneously as shown in
Table 3.
Table 3. USB Port Configuration Options
Port Configurations
OTG
OTG + 2 Hosts
OTG + 1 Host
OTG + 1 Host
OTG + 1 Peripheral
OTG + 1 Peripheral
4 Hosts
3 Hosts
2 Hosts
1 Host
Port 1A
OTG
OTG
OTG
OTG
OTG
OTG
Host
Port 1B
–
–
–
–
–
–
Host
Port 2A
–
Host
Host
–
Peripheral
–
Host
Port 2B
–
Host
–
Host
–
Peripheral
Host
Any Combination of Ports
Any Combination of Ports
Any Port
Note
2. Alternate interface location.
Document Number: 38-08015 Rev. *L
Page 4 of 112
CY7C67300
Table 3. USB Port Configuration Options
(continued)
Port Configurations
2 Hosts + 1 Peripheral
2 Hosts + 1 Peripheral
2 Hosts + 1 Peripheral
2 Hosts + 1 Peripheral
1 Host + 1 Peripheral
1 Host + 1 Peripheral
1 Host + 1 Peripheral
1 Host + 1 Peripheral
1 Host + 1 Peripheral
1 Host + 1 Peripheral
1 Host + 1 Peripheral
1 Host + 1 Peripheral
2 Peripherals
2 Peripherals
2 Peripherals
2 Peripherals
1 Peripheral
USB Features
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Port 1A
Host
Host
Peripheral
–
Host
Host
–
–
Peripheral
Peripheral
–
–
Peripheral
Peripheral
–
–
Port 1B
Host
Host
–
Peripheral
–
–
Host
Host
–
–
Peripheral
Peripheral
–
–
Peripheral
Peripheral
Any Port
Port 2A
Peripheral
–
Host
Host
Peripheral
–
–
Peripheral
Host
–
–
Host
Peripheral
–
–
Peripheral
Port 2B
–
Peripheral
Host
Host
–
Peripheral
Peripheral
–
–
Host
Host
–
–
Peripheral
Peripheral
–
OTG Interface
EZ-Host has one USB port that is compatible with the USB
On-The-Go supplement to the USB 2.0 specification. The USB
OTG port has a various hardware features to support Session
Request Protocol (SRP) and Host Negotiation Protocol (HNP).
OTG is only supported on USB PORT 1A.
OTG Features
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USB 2.0-compliant for full and low speed
Up to four downstream USB host ports
Up to two upstream USB peripheral ports
Configurable endpoint buffers (pointer and length), must reside
in internal RAM
Up to eight available peripheral endpoints (one control
endpoint)
Supports control, interrupt, bulk, and isochronous transfers
Internal DMA channels for each endpoint
Internal pull up and pull down resistors
Internal series termination resistors on USB data lines
Internal charge pump to supply and control VBUS
VBUS valid status (above 4.4V)
VBUS status for 2.4V< VBUS <0.8V
ID pin status
Switchable 2K ohm internal discharge resistor on VBUS
Switchable 500 ohm internal pull up resistor on VBUS
Individually switchable internal pull up and pull down resistors
on the USB data lines
USB Pins
Table 4. USB Interface Pins
Pin Name
DM1A
DP1A
DM1B
DP1B
DM2A
DP2A
DM2B
DP2B
Pin Number
22
23
18
19
9
10
4
5
OTG Pins
Table 5. OTG Interface Pins
Pin Name
DM1A
DP1A
OTGVBUS
OTGID
CSwitchA
CSwitchB
Pin Number
22
23
11
41
13
12
Document Number: 38-08015 Rev. *L
Page 5 of 112
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