CY7C1623KV18
144-Mbit DDR-II SIO SRAM Two-Word
Burst Architecture
144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture
Features
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Configuration
CY7C1623KV18 – 8 M × 18
144-Mbit density (8 M × 18)
333 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Synchronous internally self timed writes
DDR-II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR-I device with 1 cycle read latency
when DOFF is asserted LOW
1.8 V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4 V–V
DD
)
❐
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball FBGA package (15 × 17 × 1.4 mm)
Offered in Pb-free package
JTAG 1149.1 compatible test access port
Phase Locked Loop (PLL) for accurate data placement
Functional Description
The CY7C1623KV18 is 1.8 V Synchronous Pipelined SRAM,
equipped with DDR-II SIO (Double Data Rate Separate I/O)
architecture. The DDR-II SIO consists of two separate ports: the
read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. The DDR-II
SIO has separate data inputs and data outputs to completely
eliminate the need to ‘turnaround’ the data bus required with
common I/O devices. Access to each port is accomplished
through a common address bus. Addresses for read and write
are latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read data
is driven on the rising edges of C and C if provided, or on the
rising edge of K and K if C/C are not provided. Each address
location is associated with two 18-bit words that burst
sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR-II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
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Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
× 18
333 MHz
333
650
250 MHz
250
560
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-44276 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 28, 2013
CY7C1623KV18
Logic Block Diagram – CY7C1623KV18
D
[17:0]
18
Write Add. Decode
Read Add. Decode
A
(21:0)
22
Address
Register
Write
Data Reg
Write
Data Reg
4M x 18 Array
4M x 18 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
R/W
V
REF
LD
BWS
[1:0]
Control
Logic
CLK
Gen.
Read Data Reg.
36
18
18
Reg.
Reg.
Reg. 18
18
CQ
18
Q
[17:0]
Document Number: 001-44276 Rev. *G
Page 2 of 28
CY7C1623KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 6
Single Clock Mode ...................................................... 6
DDR Operation ............................................................ 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 7
Truth Table ........................................................................ 8
Write Cycle Descriptions ................................................. 8
IEEE 1149.1 Serial Boundary Scan (JTAG) .................... 9
Disabling the JTAG Feature ........................................ 9
Test Access Port ......................................................... 9
Performing a TAP Reset ............................................. 9
TAP Registers ............................................................. 9
TAP Instruction Set ..................................................... 9
TAP Controller State Diagram ....................................... 11
TAP Controller Block Diagram ...................................... 12
TAP Electrical Characteristics ...................................... 12
TAP AC Switching Characteristics ............................... 13
TAP Timing and Test Conditions .................................. 14
Identification Register Definitions ................................ 15
Scan Register Sizes ....................................................... 15
Instruction Codes ........................................................... 15
Boundary Scan Order .................................................... 16
Power Up Sequence in DDR-II SRAM ........................... 17
Power Up Sequence ................................................. 17
PLL Constraints ......................................................... 17
Maximum Ratings ........................................................... 18
Operating Range ............................................................. 18
Electrical Characteristics ............................................... 18
DC Electrical Characteristics ..................................... 18
AC Electrical Characteristics ..................................... 19
Capacitance .................................................................... 19
Thermal Resistance ........................................................ 19
AC Test Loads and Waveforms ..................................... 19
Switching Characteristics .............................................. 20
Switching Waveforms .................................................... 22
Ordering Information ...................................................... 23
Ordering Code Definitions ......................................... 23
Package Diagram ............................................................ 24
Acronyms ........................................................................ 25
Document Conventions ................................................. 25
Units of Measure ....................................................... 25
Document History Page ................................................. 26
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC Solutions ......................................................... 28
Document Number: 001-44276 Rev. *G
Page 3 of 28
CY7C1623KV18
Pin Configurations
The pin configuration for CY7C1623KV18 follows:
[1]
Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1623KV18 (8 M × 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Note
1. NC/288M is not connected to the die and can be tied to any voltage level.
Document Number: 001-44276 Rev. *G
Page 4 of 28
CY7C1623KV18
Pin Definitions
Pin Name
D
[17:0]
LD
I/O
Pin Description
Input-
Data Input Signals.
Sampled on the rising edge of K and K clocks during valid write operations.
Synchronous
Input-
Synchronous Load.
This input is brought LOW when a bus cycle sequence is defined. This definition
Synchronous includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period
of bus activity).
Input-
Byte Write Select 0 and 1
Active LOW.
Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Input-
Address Inputs.
Sampled on the rising edge of the K clock during active read and write operations.
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 8 M × 18 (2 arrays each of 4 M × 18). Therefore, only 22 address inputs are needed to
access the entire memory array. These inputs are ignored when the appropriate port is deselected.
Outputs-
Data Output Signals.
These pins drive out the requested data during a read operation. Valid data is
Synchronous driven out on the rising edge of both the C and C clocks during read operations, or K and K when in
single clock mode. When the read port is deselected, Q
[17:0]
are automatically tri-stated.
Input-
Synchronous Read/Write Input.
When LD is LOW, this input designates the access type (read when
Synchronous R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times
around the edge of K.
Input Clock
Positive Input Clock for Output Data.
C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See
Application Example on page 7
for further details.
Negative Input Clock for Output Data.
C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See
Application Example on page 7
for further details.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[17:0]
when in single clock mode. All accesses are initiated on the rising
edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs being presented to the device
and to drive out data through Q
[17:0]
when in single clock mode.
CQ Referenced with Respect to C.
This is a free-running clock and is synchronized to the input clock
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the
Switching Characteristics on page 20.
CQ Referenced with Respect to C.
This is a free-running clock and is synchronized to the input clock
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the
Switching Characteristics on page 20.
Output Impedance Matching Input.
This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q
[17:0]
output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
PLL Turn Off
Active LOW.
Connecting this pin to ground turns off the PLL inside the device. The
timing in the PLL turned off operation differs from those listed in this data sheet. For normal operation,
this pin can be connected to a pull up through a 10-Kohm or less pull up resistor. The device behaves
in DDR-I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of
up to 167 MHz with DDR-I timing.
BWS
0
,
BWS
1
A
Q
[17:0]
R/W
C
C
Input Clock
K
Input Clock
K
CQ
Input Clock
Echo Clock
CQ
Echo Clock
ZQ
Input
DOFF
Input
Document Number: 001-44276 Rev. *G
Page 5 of 28
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