CY14C512I
CY14B512I
CY14E512I
512-Kbit (64 K × 8) Serial (I
2
C) nvSRAM
with Real Time Clock
512-Kbit (64 K × 8) Serial (I
2
C) nvSRAM with Real Time Clock
Features
512-Kbit nonvolatile static random access memory (nvSRAM)
❐
Internally organized as 64 K × 8
❐
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I
2
C
command (Software STORE) or HSB pin (Hardware STORE)
❐
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by I
2
C command (Software RECALL)
❐
Automatic STORE on power-down with a small capacitor
■
High reliability
❐
Infinite read, write, and RECALL cycles
❐
1 million STORE cycles to QuantumTrap
❐
Data retention: 20 years at 85
C
■
Real Time Clock (RTC)
❐
Full-featured RTC
❐
Watchdog timer
❐
Clock alarm with programmable interrupts
❐
Backup power fail indication
❐
Square wave output with programmable frequency (1 Hz,
512 Hz, 4096 Hz, 32.768 kHz)
❐
Capacitor or battery backup for RTC
❐
Backup current of 0.45 µA (typical)
2
[1]
■
High-speed I C interface
❐
Industry standard 100 kHz and 400 kHz speed
❐
Fast mode Plus 1 MHz speed
❐
High speed 3.4 MHz
❐
Zero cycle delay reads and writes
■
Write protection
❐
Hardware protection using Write Protect (WP) pin
❐
Software block protection for one-quarter, one-half, or entire
array
■
■
I
2
C access to special functions
❐
Nonvolatile STORE/RECALL
❐
8-byte serial number
❐
Manufacturer ID and Product ID
❐
Sleep mode
Low power consumption
❐
Average active current of 1 mA at 3.4 MHz operation
❐
Average standby mode current of 250 µA
❐
Sleep mode current of 8 µA
Industry standard configurations
❐
Operating voltages:
• CY14C512I: V
CC
= 2.4 V to 2.6 V
• CY14B512I: V
CC
= 2.7 V to 3.6 V
• CY14E512I: V
CC
= 4.5 V to 5.5 V
❐
Industrial temperature
❐
16-pin small outline integrated circuit (SOIC) package
❐
Restriction of hazardous substances (RoHS) compliant
■
■
Overview
The Cypress CY14C512I/CY14B512I/CY14E512I combines a
512-Kbit nvSRAM
[2]
with a full-featured RTC in a monolithic
integrated circuit with serial I
2
C interface. The memory is
organized as 64 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cells provide highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down.
On power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL
operations can also be initiated by the user through I
2
C
commands.
Logic Block Diagram
V
CC
V
CAP
V
RTCcap
V
RTCbat
Serial Number
8x8
Manufacturer ID /
Product ID
Memory Control Register
Command Register
Sleep
Quantum Trap
64 K x 8
SRAM
64 K x 8
STORE
RECALL
Power Control
Block
SDA
SCL
A2, A1, A0
WP
I C Control Logic
Slave Address
Decoder
2
Control Registers Slave
Memory Slave
RTC Slave
Memory
Address and Data
Control
X
in
INT/SQW
X
out
RTC Control Logic
Registers
Counters
Notes
1. The I
2
C nvSRAM is a single solution which is usable for all four speed modes of operation. As a result, some I/O parameters are slightly different than those on
chips which support only one mode of operation. Refer to
AN87209
for more details.
2. Serial (I
2
C) nvSRAM will be referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation
Document Number: 001-64879 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 30, 2013
CY14C512I
CY14B512I
CY14E512I
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
I2C Interface ...................................................................... 4
Protocol Overview ............................................................ 4
I2C Protocol – Data Transfer ....................................... 4
Data Validity ................................................................ 5
START Condition (S) ................................................... 5
STOP Condition (P) ..................................................... 5
Repeated START (Sr) ................................................. 5
Byte Format ................................................................. 5
Acknowledge / No-acknowledge ................................. 5
High-Speed Mode (Hs-mode) ..................................... 6
Slave Device Address ................................................. 7
Write Protection (WP) .................................................. 9
AutoStore Operation .................................................... 9
Hardware STORE and HSB pin Operation ................. 9
Hardware RECALL (Power Up) ................................... 9
Write Operation ......................................................... 10
Read Operation ......................................................... 10
Memory Slave Access ............................................... 10
RTC Registers Slave Access .................................... 14
Control Registers Slave ............................................. 16
Serial Number ................................................................. 18
Serial Number Write .................................................. 18
Serial Number Lock ................................................... 18
Serial Number Read .................................................. 18
Device ID ......................................................................... 19
Executing Commands Using Command Register ..... 19
Real Time Clock Operation ............................................ 20
nvTIME Operation ..................................................... 20
Clock Operations ....................................................... 20
Reading the Clock ..................................................... 20
Setting the Clock ....................................................... 20
Backup Power ........................................................... 20
Stopping and Starting the Oscillator .......................... 20
Calibrating the Clock ................................................. 21
Alarm ......................................................................... 21
Watchdog Timer ........................................................ 21
Programmable Square Wave Generator ................... 22
Power Monitor ........................................................... 22
Backup Power Monitor .............................................. 22
Interrupts ................................................................... 22
Interrupt Register ....................................................... 22
Flags Register ........................................................... 23
Maximum Ratings ........................................................... 29
Operating Range ............................................................. 29
DC Electrical Characteristics ........................................ 29
Data Retention and Endurance ..................................... 30
Thermal Resistance ........................................................ 30
AC Test Loads and Waveforms ..................................... 31
AC Test Conditions ........................................................ 31
RTC Characteristics ....................................................... 31
AC Switching Characteristics ....................................... 32
Switching Waveforms .................................................... 32
nvSRAM Specifications ................................................. 33
Switching Waveforms .................................................... 33
Software Controlled STORE/RECALL Cycles .............. 34
Switching Waveforms .................................................... 34
Hardware STORE Cycle ................................................. 35
Switching Waveforms .................................................... 35
Ordering Information ...................................................... 36
Ordering Code Definitions ......................................... 36
Package Diagram ............................................................ 37
Acronyms ........................................................................ 38
Document Conventions ................................................. 38
Units of Measure ....................................................... 38
Document History Page ................................................. 39
Sales, Solutions, and Legal Information ...................... 40
Worldwide Sales and Design Support ....................... 40
Products .................................................................... 40
PSoC Solutions ......................................................... 40
Document Number: 001-64879 Rev. *G
Page 2 of 41
CY14C512I
CY14B512I
CY14E512I
Pinout
Figure 1. 16-pin SOIC pinout
NC
VRTCbat
Xout
Xin
WP
A0
V
RTCcap
V
SS
1
2
3
4
5
6
7
8
Top View
not to scale
12
11
10
9
SDA
SCL
A1
HSB
16
15
14
13
V
CC
INT/SQW
V
CAP
A2
Pin Definitions
Pin Name
SCL
SDA
WP
A2–A0
HSB
I/O Type
Input
Description
Clock: Runs at speeds up to a maximum of f
SCL
.
Input/Output I/O: Input/output of data through I
2
C interface.
Output: Is open-drain and requires an external pull-up resistor.
Input
Input
Write Protect: Protects the memory from all writes. This pin is internally pulled LOW and hence can be
left open if not connected.
Slave Address: Defines the slave address for I
2
C. These pins are internally pulled LOW and hence can
be left open if not connected.
Input/Output Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (t
HHHD
) with standard output high current and then a weak
internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
Power supply AutoStore capacitor: Supplies power to the nvSRAM during power loss to STORE data from the SRAM
to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as No Connect. It
must never be connected to ground.
Power supply Battery backup for RTC: Left unconnected if V
RTCcap
is used.
Output
Input
[3]
V
CAP
V
RTCcap[3]
Power supply Capacitor backup for RTC: Left unconnected if V
RTCbat
is used.
V
RTCbat[3]
X
out[3]
X
in[3]
INT/SQW
Crystal output connection
Crystal input connection
Interrupt output/calibration/square wave. Programmable to respond to the clock alarm, the watchdog
timer, and the power monitor. Also programmable to either active HIGH (push or pull) or LOW (open
drain). In Calibration mode, a 512 Hz square wave is driven out. In Square Wave mode, the user may
select a frequency of 1 Hz, 512 Hz, 4096 Hz, or 32768 Hz to be used as a continuous output.
No connect. This pin is not connected to the die.
Output
NC
V
SS
V
CC
No connect
Power supply Ground
Power supply Power supply
Note
3. Left unconnected if RTC feature is not used.
Document Number: 001-64879 Rev. *G
Page 3 of 41
CY14C512I
CY14B512I
CY14E512I
I
2
C
Interface
I
2
C bus consists of two lines – serial clock line (SCL) and serial
data line (SDA) – that carry information between multiple devices
on the bus. I
2
C supports multi-master and multi-slave
configurations. The data is transmitted from the transmitter to the
receiver on the SDA line and is synchronized with the clock SCL
generated by the master.
The SCL and SDA lines are open-drain lines and are pulled up
to V
CC
using resistors. The choice of a pull-up resistor on the
system depends on the bus capacitance and the intended speed
of operation. The master generates the clock, and all the data
I/Os are transmitted in synchronization with this clock. The
CY14X512I supports up to 3.4 MHz clock speed on SCL line.
slave address and eighth bit (R/W) indicating a read (1) or a write
(0) operation. All signals are transmitted on the open-drain SDA
line and are synchronized with the clock on SCL line. Each byte
of data transmitted on the I
2
C bus is acknowledged by the
receiver by holding the SDA line LOW on the ninth clock pulse.
The request for write by the master is followed by the memory
address and data bytes on the SDA line. The writes can be
performed in burst-mode by sending multiple bytes of data. The
memory address increments automatically after the
receive/transmit of each byte on the falling edge of the ninth
clock cycle. The new address is latched just prior to
sending/receiving the acknowledgment bit. This allows the next
sequential byte to be accessed with no additional addressing. On
reaching the last memory location, the address rolls back to
0x0000 and writes continue. The slave responds to each byte
sent by the master during a write operation with an ACK. A write
sequence can be terminated by the master generating a STOP
or Repeated START condition.
A read request is performed at the current address location
(address next to the last location accessed for read or write). The
memory slave device responds to a read request by transmitting
the data on the current address location to the master. A random
address read may also be performed by first sending a write
request with the intended address of read. The master must
abort the write immediately after the last address byte and issue
a Repeated START or STOP signal to prevent any write
operation. The following read operation starts from this address.
The master acknowledges the receipt of one byte of data by
holding the SDA pin LOW for the ninth clock pulse. The reads
can be terminated by the master sending a no-acknowledge
(NACK) signal on the SDA line after the last data byte. The NACK
signal causes the CY14X512I to release the SDA line and the
master can then generate a STOP or a Repeated START
condition to initiate a new operation.
Protocol Overview
This device supports only a 7-bit addressable scheme. The
master generates a START condition to initiate the
communication followed by broadcasting a slave select byte.
The slave select byte consists of a 7-bit slave address that the
master intends to communicate with and R/W bit indicating a
read or a write operation. The selected slave responds to this
with an acknowledgement (ACK). After a slave is selected, the
remaining part of the communication takes place between the
master and the selected slave device. The other devices on the
bus ignore the signals on the SDA line until a STOP or Repeated
START condition is detected. The data transfer is done between
the master and the selected slave device through the SDA pin
synchronized with the SCL clock generated by the master.
I
2
C
Protocol – Data Transfer
Each transaction in I
2
C protocol starts with the master
generating a START condition on the bus, followed by a 7-bit
Figure 2. System Configuration using Serial (I
2
C) nvSRAM
Vcc
R
Pmin
= (V
CC
- V
OL
max) / I
OL
R
Pmax
= t
r
/ (0.8473 * C
b
)
SDA
Microcontroller
SCL
Vcc
Vcc
A0
A1
A2
SCL
SDA
WP
A0
A1
A2
SCL
SDA
WP
A0
A1
A2
SCL
SDA
WP
CY14X512I
#0
CY14X512I
#1
CY14X512I
#7
Document Number: 001-64879 Rev. *G
Page 4 of 41
CY14C512I
CY14B512I
CY14E512I
Data Validity
The data on the SDA line must be stable during the HIGH period
of the clock. The state of the data line can only change when the
clock on the SCL line is LOW for the data to be valid. There are
only two conditions under which the SDA line may change state
with SCL line held HIGH: START and STOP condition. The
START and STOP conditions are generated by the master to
signal the beginning and end of a communication sequence on
the I
2
C bus.
STOP Condition (P)
A LOW to HIGH transition on the SDA line while SCL is HIGH
indicates a STOP condition. This condition indicates the end of
the ongoing transaction.
START and STOP conditions are always generated by the
master. The bus is considered to be busy after the START
condition. The bus is considered to be free again after the STOP
condition.
START Condition (S)
A HIGH to LOW transition on the SDA line while SCL is HIGH
indicates a START condition. Every transaction in I
2
C begins
with the master generating a START condition.
Repeated START (Sr)
If a Repeated START condition is generated instead of a STOP
condition, the bus continues to be busy. The ongoing transaction
on the I
2
C lines is stopped and the bus waits for the master to
send a slave ID for communication to restart.
Figure 3. START and STOP Conditions
full pagewidth
SDA
SDA
SCL
S
START Condition
P
STOP Condition
SCL
Figure 4. Data Transfer on the I
2
C Bus
handbook, full pagewidth
P
Sr
SDA
MSB
Acknowledgement
signal from slave
Acknowledgement
signal from receiver
SCL
S
or
Sr
1
2
7
8
9
ACK
1
2
3-8
9
ACK
Sr
or
P
STOP or
Repeated START
condition
START or
Repeated START
condition
Byte complete,
interrupt within slave
Clock line held LOW while
interrupts are serviced
Byte Format
Each operation in I
2
C is done using 8-bit words. The bits are sent
in MSB first format on SDA line and each byte is followed by an
ACK signal by the receiver.
An operation continues till a NACK is sent by the receiver or
STOP or Repeated START condition is generated by the master
The SDA line must remain stable when the clock (SCL) is HIGH
except for a START or STOP condition.
does not acknowledge the receipt of data and the operation is
aborted.
NACK can be generated by master during a READ operation in
following cases:
■
■
The master did not receive valid data due to noise.
The master generates a NACK to abort the READ sequence.
After a NACK is issued by the master, nvSRAM slave releases
control of the SDA pin and the master is free to generate a
Repeated START or STOP condition.
Acknowledge / No-acknowledge
After transmitting one byte of data or address, the transmitter
releases the SDA line. The receiver pulls the SDA line LOW to
acknowledge the receipt of the byte. Every byte of data
transferred on the I
2
C bus needs a response with an ACK signal
by the receiver to continue the operation. Failing to do so is
considered as a NACK state. NACK is the state where receiver
NACK can be generated by nvSRAM slave during a WRITE
operation in these cases:
■
■
nvSRAM did not receive valid data due to noise.
The master tries to access write protected locations on the
nvSRAM. Master must restart the communication by
generating a STOP or Repeated START condition.
Document Number: 001-64879 Rev. *G
Page 5 of 41
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