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Bt8230
ATM Segmentation and
Reassembly Controller-SAR
data sheet
PROVIDING
HIGH
SPEED
MULTIMEDIA
CONNECTIONS
Because
Communication
Matters
™
Bt8230
ATM Segmentation and Reassembly Controller—SAR
The Bt8230 Segmentation and Reassembly Controller (SRC) incorporates a host
interface, ATM Adaptation Layer processing, and line interfaces in a single device.
The feature set includes a PCI bus interface, segmentation and reassembly control-
lers, a local memory controller, a DMA coprocessor, and an automatic scheduling
algorithm. Each segmentation channel manages an independent bit rate of up to 200
Mbps per channel for simplex connections. This feature set makes the Bt8230 ideal
for file server ATM adapters, routers/hubs, and other Wide Area Network (WAN)
applications. The PCI bus interface makes the SRC suitable for workstation network
interface cards (NICs) as well.
The Bt8230 supports sixteen thousand open connections simultaneously with
robust Operation and Maintenance (OAM), signaling, and Interim Local Management
Interface (ILMI) features. Other key features include support for random Virtual Path
Indicator/Virtual Channel Indicator (VPI/VCI) assignment, interleaved AAL5 and
AAL3/4 Segmentation and Reassembly (SAR), and termination of signaling and ILMI
into local memory to maintain management connections independently. The Bt8230
fulfills all the requirements of the ATM Forum UNI 3.1 standards and the related ANSI
and ITU standards. The device is pin-compatible with the Bt8233 SRC which sup-
ports new traffic management algorithms for ABR service as defined in TM 4.0.
The Bt8230 architecture provides several implementation options, allowing users
to balance the cost and functions of their systems. In stand-alone mode, the Bt8230
is capable of full line-rate performance, presenting a low-cost option ideal for work-
station ATM NICs. Combined with the Bt8222 ATM Receiver/Transmitter, the Bt8230
delivers an ATM solution capable of full-duplex operation at 155.52 Mbps without the
cost constraints of using a large amount of local memory to buffer incoming ATM
cells. When using the local processor, host driver software needs decrease and host
performance is improved since more control functions are handled locally. In slave
UTOPIA mode, the Bt8230 can be connected directly to an ATM backplane for appli-
cations exceeding 155 Mbps.
The Bt8230EVS evaluation system provides a working reference design and an
example software driver. It also has facilities for generating and terminating ATM traf-
fic.
Distinguishing Features
•
•
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•
•
•
•
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•
•
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Simultaneous ATM and SMDS SAR
ATM Forum UNI 3.1 compliant
Pin-compatible with TM 4.0 options
AAL0, AAL3/4, and AAL5 SAR
Formats AAL3/4 and AAL5 CPCS fields
and performs all checks
Performance monitoring per GR-1248
and ITU I.610, dated 3/93
Supports 16,384 active Virtual Circuit
Channels (VCCs)
Robust per-VCC statistics supports
SNMP MIB requirements
Internal MIB counters
155 Mbps full-duplex throughput
UTOPIA master, UTOPIA slave, or
Bt8222-compatible ATM PHY interface
PCI host interface (master and slave
mode), Revision 2.0
Automatic scheduling algorithm oper-
ates individually on each channel
Host or local segmentation and
reassembly
VBR and UBR traffic types
Scatter/gather DMA to host memory
Optional local processor for signaling,
OAM, and ILMI management functions
Zero- or one-wait-state local memory
Boundary scan to facilitate board-level
testing
Low-power CMOS process in a
208-pin PQFP
Complete working reference design,
software, and documentation package
available
Functional Block Diagram
32
Local
Processor
Bus
Control/
Status
Cell
FIFO
UTOPIA or
Bt8222 ATM
Interface Rx/Tx
Applications
• ATM interface for routers and hubs
• ATM/PCI interface cards
• Test and WAN equipment
• Service access multiplexors
Timer
Counters
32
PCI
Bus
Memory
Arbiter
Reassembler
Segmenter
Scheduler
P
C
I
D
M
A
Bt8230
Ordering Information
Model Number
Bt8230EPFC
Manufacturing
Part Number
28230-13
Product
Revision
C
Package
208-pin PQFP
Operating Temperature
-40
°
C to 85
°
C
Copyright © 1998 Rockwell Semiconductor Systems, Inc. All rights reserved.
Print date: March 1998
Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve
performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no
responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by its implication or otherwise under any patent or intellectual property rights of Rockwell
Semiconductor Systems, Inc.
Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or
systems where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal
injury or death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc.
products for use in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc.
for any damages resulting from such improper use or sale.
®
Bt is a registered trademark of Rockwell Semiconductor Systems, Inc. SLC is a registered trademark of AT&T Technologies,
Inc. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
Table of Contents
List of Figures.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
1.0 Product Description.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Components of the Bt8230
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.1 DMA Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 Segmentation Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.3 Reassembly Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.4 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.5 Local Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.6 Local Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.7 ATM Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
4
4
4
5
5
1.2 Logic Diagram and Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.0 Bt8230 Architecture Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Queue and Buffer Architecture.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1 Queue Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
2.1.2 Status Queue Relation to Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
2.2 Automated Segmentation Engine.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Automated Reassembly Engine
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Traffic Scheduling
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.1 Traffic Management Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
2.4.2 VBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
2.4.3 UBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
2.5 Implementation of OAM-PM Protocols
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6 Standards-Based I/O.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6.1 PCI Bus I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 ATM PHY I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.3 Local Memory I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.4 Local Processor I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.5 Boundary Scan I/O and Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
25
25
25
N8230DS1F
i
Bt8230
ATM Segmentation and Reassembly Controller—SAR
3.0 Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 DMA Coprocessor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.1 DMA Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
3.1.2 DMA Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
3.1.3 Misaligned Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
3.2 Memory Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.1 Memory Bank Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
3.3 Local Processor Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3.1 Interface Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 Bus Cycle Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2.1 Single Read Cycle, Zero Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2.2 Single Read Cycle, Wait States Inserted By Memory Arbitration . . . . . . . . . . . . .
3.3.2.3 Double Read Burst With Processor Wait States. . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2.4 Single Write With One-Wait-State Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2.5 Quad Burst Write, No Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 i80960CA/CF Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4 i80960Jx Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5 Stand-alone Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5.1 Address Mapping in Stand-Alone Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.6 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.7 Real-Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.8 Bt8230 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Memory Set Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Initialization of Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 Initializing Segmentation VCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4 Segmentation Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.5 Adding Segmentation Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.6 Descriptor Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.7 Rate-Controlled Segmentation (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.8 Unspecified Bit-Rate Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.9 Segmentation Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.10 OAM, ILMI, and Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.11 Idle Cell Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.12 ATM Header Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.13 AAL3/4 SAR-PDU Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.14 AAL5 SAR-PDU Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.15 AAL0 SAR-PDU Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.16 CRC-10 Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.17 Transmit Cell FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
36
36
38
39
40
41
42
43
43
46
46
46
47
51
52
55
57
57
59
60
63
63
63
64
65
65
66
67
67
67
3.4 Segmentation Coprocessor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.5 Reassembly Coprocessor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.5.1 Local Memory Set Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
3.5.2 Hashing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
3.5.2.1 Hashing Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
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N8230DS1F
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