电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

89HPES24T6G2ZABL

产品描述PCI Bus Controller, PBGA676, 27 X 27 MM, 1 MM PITCH, FCBGA-676
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小1MB,共50页
制造商IDT (Integrated Device Technology)
下载文档 详细参数 选型对比 全文预览 文档解析

89HPES24T6G2ZABL概述

PCI Bus Controller, PBGA676, 27 X 27 MM, 1 MM PITCH, FCBGA-676

89HPES24T6G2ZABL规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码BGA
包装说明27 X 27 MM, 1 MM PITCH, FCBGA-676
针数676
Reach Compliance Codenot_compliant
ECCN代码3A001.A.3
其他特性ALSO REQUIRES 3.3V SUPPLY
地址总线宽度
最大时钟频率125 MHz
驱动器接口标准IEEE 1149.1
外部数据总线宽度
JESD-30 代码S-PBGA-B676
JESD-609代码e0
长度27 mm
端子数量676
最高工作温度70 °C
最低工作温度
封装主体材料PLASTIC/EPOXY
封装代码BGA
封装形状SQUARE
封装形式GRID ARRAY
峰值回流温度(摄氏度)225
认证状态Not Qualified
座面最大高度3.22 mm
最大供电电压1.1 V
最小供电电压0.9 V
标称供电电压1 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式BALL
端子节距1 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间30
宽度27 mm
uPs/uCs/外围集成电路类型BUS CONTROLLER, PCI

文档解析

PES24T6G2 交换机专为嵌入式应用设计,提供紧凑、高效的 PCIe 互连。它支持 6 个下游端口的上游连接,并允许下游端口间切换,适用于资源有限的嵌入式系统。设备集成 24 个 5 Gbps SerDes,无需额外组件,降低系统复杂性和成本。 特性包括 GPIO 引脚(最多 11 个),可独立配置为输入/输出或中断;支持串行 EEPROM 配置,覆盖默认寄存器设置;功耗管理功能如 D0、D3hot 和 D3cold 状态,以及可选的 SerDes 低摆幅电压模式。测试模式包括主环回,便于在系统链路测试。 在嵌入式处理器连接中,设备优化了带宽利用率,支持跨链路操作。小型 19mm x 19mm 封装选项节省空间,而通用事件输出和复位引脚增强控制灵活性。适用于工业自动化和汽车电子等场景,提供稳定、可扩展的 I/O 解决方案。

文档预览

下载PDF文档
24-Lane 6-Port
Gen2 PCI Express® Switch
®
89HPES24T6G2
Data Sheet
Advance Information*
Device Overview
The 89HPES24T6G2 is a member of IDT’s PRECISE™ family of PCI
Express® switching solutions. The PES24T6G2 is a 24-lane, 6-port
Gen2 peripheral chip that performs PCI Express base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications systems. It provides connectivity and
switching functions between a PCI Express upstream port and up to five
downstream ports and supports switching between downstream ports.
Features
High Performance PCI Express Switch
– Twenty-four 5 Gbps Gen2 PCI Express lanes supporting
5 Gbps and 2.5 Gbps operation
– Up to six switch ports
– Support for Max Payload Size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– Fully compliant with PCI Express base specification Revision
2.0
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2, or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Supports in-band hot-plug presence detect capability
– Supports external signal for hot plug event notification allowing
SCI/SMI generation for legacy operating systems
– Dynamic link width reconfiguration for power/performance
optimization
– Configurable downstream port PCI-to-PCI bridge device
numbering
– Crosslink support
– Supports ARI forwarding defined in the Alternative Routing-ID
Interpretation (ARI) ECN for virtualized and non-virtualized
environments
– Ability to load device configuration from serial EEPROM
Legacy Support
– PCI compatible INTx emulation
– Supports bus locked transactions, allowing use of PCI Express
with legacy software
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates twenty-four 5 Gbps / 2.5 Gbps embedded SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Ability to disable peer-to-peer communications
– Supports ECRC and Advanced Error Reporting
– All internal data and control RAMs are SECDED ECC
protected
– Supports PCI Express hot-plug on all downstream ports
– Supports upstream port hot-plug
Block Diagram
6-Port Switch Core / 24 Gen2 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
SerDes SerDes
SerDes
SerDes
SerDes SerDes
SerDes
SerDes
SerDes SerDes
(Port 0)
(Port 1)
Figure 1 Internal Block Diagram
(Port 5)
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 50
©
2007 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
December 4, 2007
DSC 6930
Advance Information

89HPES24T6G2ZABL相似产品对比

89HPES24T6G2ZABL 89HPES24T6G2ZAAR 89HPES24T6G2ZAAL 89HPES24T6G2ZABR
描述 PCI Bus Controller, PBGA676, 27 X 27 MM, 1 MM PITCH, FCBGA-676 PCI Bus Controller, PBGA324, 19 X 19 MM, 1 MM PITCH, ROHS COMPLIANT, FCBGA-324 PCI Bus Controller, PBGA324, 19 X 19 MM, 1 MM PITCH, FCBGA-324 PCI Bus Controller, PBGA676, 27 X 27 MM, 1 MM PITCH, ROHS COMPLIANT, FCBGA-676
是否无铅 含铅 不含铅 含铅 不含铅
是否Rohs认证 不符合 符合 不符合 符合
零件包装代码 BGA BGA BGA BGA
包装说明 27 X 27 MM, 1 MM PITCH, FCBGA-676 BGA, BGA, BGA,
针数 676 324 324 676
Reach Compliance Code not_compliant compliant not_compliant not_compliant
ECCN代码 3A001.A.3 3A001.A.3 3A001.A.3 3A001.A.3
其他特性 ALSO REQUIRES 3.3V SUPPLY ALSO REQUIRES 3.3V SUPPLY ALSO REQUIRES 3.3V SUPPLY ALSO REQUIRES 3.3V SUPPLY
最大时钟频率 125 MHz 125 MHz 125 MHz 125 MHz
驱动器接口标准 IEEE 1149.1 IEEE 1149.1 IEEE 1149.1 IEEE 1149.1
JESD-30 代码 S-PBGA-B676 S-PBGA-B324 S-PBGA-B324 S-PBGA-B676
JESD-609代码 e0 e3 e0 e1
长度 27 mm 19 mm 19 mm 27 mm
端子数量 676 324 324 676
最高工作温度 70 °C 70 °C 70 °C 70 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 BGA BGA BGA BGA
封装形状 SQUARE SQUARE SQUARE SQUARE
封装形式 GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY
峰值回流温度(摄氏度) 225 260 225 260
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 3.22 mm 3.42 mm 3.42 mm 3.22 mm
最大供电电压 1.1 V 1.1 V 1.1 V 1.1 V
最小供电电压 0.9 V 0.9 V 0.9 V 0.9 V
标称供电电压 1 V 1 V 1 V 1 V
表面贴装 YES YES YES YES
技术 CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 Tin/Lead (Sn/Pb) Matte Tin (Sn) Tin/Lead (Sn/Pb) Tin/Silver/Copper (Sn/Ag/Cu)
端子形式 BALL BALL BALL BALL
端子节距 1 mm 1 mm 1 mm 1 mm
端子位置 BOTTOM BOTTOM BOTTOM BOTTOM
处于峰值回流温度下的最长时间 30 30 30 30
宽度 27 mm 19 mm 19 mm 27 mm
uPs/uCs/外围集成电路类型 BUS CONTROLLER, PCI BUS CONTROLLER, PCI BUS CONTROLLER, PCI BUS CONTROLLER, PCI
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) - IDT (Integrated Device Technology)
Base Number Matches - 1 1 1

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1254  413  280  1873  1822  11  14  27  51  24 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved