CA82C59A
PROGRAMMABLE INTERRUPT CONTROLLER
• Pin and functional compatibility with the
industry standard 8259/8259A
• Fully static, high speed design (10 & 8 MHz)
• Compatible with 8080/85, 8086/88, 80286/386 and
68000 family microprocessor systems
• TTL input/output compatibility
• Low power CMOS implementation
• Eight level priority controller
• Expandable to 64 levels
• Programmable interrupt modes, with each
interrupt maskable
• Edge- or level-triggered interrupt request inputs
• Polling operation
The Tundra CA82C59A is a high performance, completely
programmable interrupt controller. It can process eight inter-
rupt request inputs, assigning a priority level to each one, and
is cascadable up to 64 interrupt requests. Individual interrupt-
ing sources are maskable. Its two modes of operation (Call
and Vector) allow it to be used with virtually all 8000 and
80000 type processors, as well as with the 68000 family of
microprocessors.
Featuring fully static, very high speed operation, the
CA82C59A is designed to relieve the system CPU from
polling in a multi-level priority interrupt system.
2
2.6
CA82C59A
VDD
WR
RD
A0
INTA
CS
D7
CS
WR
RD
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CAS
0
CAS
1
V
SS
D6
D5
D4
D3
D2
D1
D0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
25
24
23
IR7
IR6
IR5
IR4
IR3
IR2
IR1
CA82C59A
22
21
20
19
CAS0
CAS1
CAS2
SP / EN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
27
26
V
DD
A
0
INTA
IR
7
IR
6
IR
5
IR
4
IR
3
IR
2
IR
1
IR
0
INT
SP/EN
CAS
2
4
3
2
1
CA82C59A
VSS
Figure 2-1: PLCC Pin Configurations
INT
IR0
Figure 2-2: PDIP/SOIC Pin Configurations
Tundra Semiconductor Corporation
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Tundra Semiconductor Corporation
CA82C59A
Table 2-1: Pin Descriptions
Pins
Symbol
PLCC
A
0
27
PDIP
27
I
It is used by the CA82C59A to decipher various command words written by the CPU,
and Status information read by the CPU. It is typically connected to the CPU - A
0
address line.
Cascade Line: These signals are outputs for the master CA82C59A, and inputs for
slaved CA82C59As. The CAS lines are used as a private bus by a CA82C59A master to
control a multiple CA82C59A system structure.
Chip Select: An active LOW signal used to enable
RD
and
WR
communication between
the CPU and the CA82C59A. Note that
INTA
functions are independent of
CS
.
Data Bus: Bi-directional, tri-state, 8-bit data bus for the transfer of control, status and
interrupt vector information.
Interrupt: This signal goes HIGH when a valid interrupt request is asserted. It is used to
interrupt the CPU, and is thus connected to the CPU interrupt pin.
Interrupt Acknowledge: Signal used to enable the CA82C59A interrupt vector data onto
the data bus by a sequence of interrupt acknowledge pulses issued by the CPU.
Interrupt Requests: Asynchronous input signals, an interrupt request is executed by
raising an IR input (LOW to HIGH), and holding it HIGH until it is acknowledged
(Edge Triggered Mode), or just by a HIGH level on an IR input (Level Triggered
Mode).
Read: Active LOW signal used to enable the CA82C59A to output status information
onto the data bus for the CPU, when CS is LOW.
Slave Program/Enable Buffer: Active LOW, dual function control signal. When in the
Buffered Mode, it can be used as an output to control buffer transceivers (
EN
). When
not in the buffered mode it can be used as an input to designate a master (SP = 1) or a
slave (SP = 0).
Power: 5 v
±
10% DC Supply
Ground: 0 v
Write: Active LOW signal used to enable the CA82C59A to accept command words
from the CPU, when
CS
is LOW.
Type
Name and Function
CAS
0-2
12, 13,
15
1
4 - 11
17
26
12, 13,
15
1
4 - 11
17
26
I/O
CS
I
I/O
O
I
D
7
- D
0
INT
INTA
IR
0-7
18 - 25
18 - 25
I
RD
3
3
I
SP
/
EN
16
16
I/O
V
DD
V
SS
WR
28
14
2
28
14
2
-
-
I
Tundra Semiconductor Corporation
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CA82C59A
Tundra Semiconductor Corporation
FUNCTIONAL DESCRIPTION
The CA82C59A Programmable Interrupt Controller is
designed for use in interrupt driven micro-computer systems.
Acting as an overall peripherals manager, its functions
include:
•
•
•
Accepting interrupt requests from assorted peripheral
devices
Determining which is the highest priority
Establishing whether or not the new interrupt is of a
higher priority than any interrupts which might be
currently being serviced, and if so,
Issuing an interrupt to the CPU
Then providing the CPU with the interrupt service
routine address of the interrupting peripheral
•
I/O peripheral.
The major functional components of the CA82C59A are laid
out in the block diagram of Figure 2-3. Vector data and de-
vice programming information are transferred from the sys-
tem bus to the CA82C59A via the 3-state, bi-directional Data
Bus Buffer which is connected to the internal bus of the con-
troller. Control data between the CA82C59A and the CPU,
and between master and slave CA82C59A devices, is man-
aged by one of three functional blocks:
•
•
The Read/Write Control block processes CPU initiated
reads and writes to the CA82C59A registers
The Control Logic block receives and generates the
signals that control the sequence of events during an
interrupt
The Cascade Control block is used to operate a private
bus (CAS
0
- CAS
2
) connecting master and slave
CA82C59As in those systems having cascaded
CA82C59As.
•
•
Each peripheral device usually has a specific interrupt service
routine which is particular to its operational or functional
requirements within the system. The CA82C59A can be
programmed to hold a pointer to the service routine addresses
associated with each of the peripheral devices under its
control. Thus when a peripheral interrupt is passed through to
the CPU, the CA82C59A can set the CPU Program Counter
to the interrupt service routine required. These pointers (or
vectors) are addresses in a vector table.
The CA82C59A is intended to run in one of two major
operational modes, according the type of CPU being used in
the system. The CALL Mode is used for 8085 type
microprocessor systems, while the VECTOR Mode is
reserved for those systems using more sophisticated
processors such as the 8088/86, 80286/386 or 68000 family.
In either mode, the CA82C59A can manage up to eight
interrupt request levels individually, with a maximum
capability of up to 64 interrupt request levels when cascaded
with other CA82C59As. A selection of priority modes is also
available such that interrupt requests can be processed in a
number of different ways to meet the requirements of a
variety of system configurations.
Priority modes can be changed or reconfigured dynamically
at any time during system operation using the operation
command words (OCWs), allowing the overall interrupt
structure to be defined for a complete system. Note that the
CA82C59A is programmed by the system software as an
Programming data passed over the system bus is saved in the
Initialization and Command Word Registers. Note that the
contents of these registers cannot be read back by the CPU.
Peripheral interrupt requests (IR
0
- IR
7
) are handled by the
functional blocks comprising the Interrupt Request Register
(IRR), the Interrupt Mask Register (IMR), the In-Service
Register (ISR) and the Priority Decision Logic block.
Interrupt requests are received at the IRR, the IMR masks
those interrupts which cannot be accepted by the CA82C59A,
and the ISR shows those interrupt requests which are
currently being processed. These three registers can all be
read by the CPU under software control. The Priority
Decision Logic block determines which interrupt will be
processed next according to a variety of indicators which
include the current priority, mode status, current interrupt
mask and interrupt service status.
The actual operation of the CA82C59A and its many modes
are described in the section following device specifications
and characteristics.
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Tundra Semiconductor Corporation
Tundra Semiconductor Corporation
Table 2-2: AC Characteristics (T
A
= -40° to +85°C, V
DD
= 5V
±
10%)
Symbol
t
AHDV
t
AHRL
t
AHWL
t
CHCL
t
CVDV
t
CVIAL
t
DVWH
t
IAIAH
t
IAIAL
t
IALCV
t
JHIH
t
JLJH
t
RHAX
t
RHDZ
t
RHEH
t
RHRL
t
RLDV
t
RLEL
t
RLRH
t
RV1
t
RV2
t
WHAX
t
WHDX
t
WHWL
t
WLWH
Notes:
CA82C59A
Parameter
Data valid from stable address
A
0
/
CS
setup to
RD
/
INTA
↓
A
0
/
CS
setup to
WR
↓
End of Command to next Command (Not same command
type) End of
INTA
sequence to next
INTA
sequence (same as
t
RV2
)
Cascade valid to valid data
Cascade setup to second or third
INTA
↓
(slave only)
Data setup to
WR
↑
INTA
INTA
Limits (8 MHz) Limits (10 MHz)
Test
Conditions
Min
Max
Min
Max
Note 5
-
5
5
Note 1
Note 5
Slave
160
INTA
Units
ns
ns
ns
ns
ns
ns
200
-
-
-
200
-
100
-
100
260
200
-
0
85
50
-
120
100
100
-
-
0
0
100
100
-
5
5
160
-
30
-
100
-
-
-
100
-
10
-
100
-
-
-
100
100
-
-
-
-
160
-
-
-
130
-
ns
-
ns
160
120
-
ns
65
50
-
95
70
ns
-
-
ns
ns
ns
ns
200
-
40
-
160
-
-
-
100
-
10
-
160
pulse width HIGH
pulse width LOW
Sequence
160
Note 5
Note 5
Note 2
0
Note 6
Note 5
ns
Cascade valid from first
INTA
↓
(master only)
Interrupt output delay
Interrupt request width (LOW)1
A
0
/
CS
hold after
RD
/
INTA
↑
Data float after
RD
/
INTA
↑
Enable inactive from
RD
↑
or
INTA
↑
End of
RD
to next
RD
End of INTA to next
INTA
within an
INTA
sequence only
Data valid from
RD
/
INTA
↓
Enable active from
RD
↓
or
INTA
↓
RD
ns
ns
ns
ns
ns
ns
ns
ns
Note 5
Note 5
160
Note 3
Note 4
0
0
160
160
-
-
-
200
200
-
-
-
-
pulse width
Command recovery time
INTA
ns
ns
recovery time
A
0
/
CS
hold after
WR
↑
Data hold after
WR
↑
End of
WR
to next
WR
WR
pulse width
1. The time to move
INTA
to/from command (read/write).
2. The time to clear the input latch in edge-triggered mode.
3. The time to move from read to write operation.
4. The time to move to the next
INTA
operation.
5. See Figure 2-6, Note 5 for load circuit values.
6. See Figure 2-6, Note 6 for load circuit values.
Tundra Semiconductor Corporation
2-127
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