8 - B IT S E R IA L - P A R A L L E L S H IFT R E GIS T E R
SERIAL
DATA OUT
V
DD
5
V
S S
4
L A TC H E S
7
STROBE
OUTPUT ENABLE
(ACTIVE LOW)
8
MOS
Bipolar
Sub
1
V
E E
9
K
10
OUT OUT OUT OUT OUT OUT OUT OUT
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11
May 2006
2
M9999-050506
(408) 955-1690
Micrel, Inc.
MIC5841/42
Absolute Maximum Ratings
(1,2,3)
At 25°C Free-Air Temperature and V
SS
................... 0V
Output Voltage, V
CE
(MIC5841) ............................. 50V
(MIC5842) .............................. 80V
Output Voltage, V
CE(SUS)
(MIC5841)
(1)..................................
35V
(MIC5842) ........................ 50V
Logic Supply Voltage, V
DD
....................................... 15V
VDD with Reference to V
EE
..................................... 25V
Emitter Supply Voltage, V
EE
...................................–20V
Input Voltage Range, V
IN
............... –0.3V to V
DD
+ 0.3V
Continuous Output Current, I
OUT
.........................500mA
Package Power Dissipation, P
D
(2)
........................1.82W
Operating Temperature Range, T
A
.......–55°C to +85°C
Storage Temperature Range, T
S
........–65°C to +150°C
Electrical Characteristics
At T
A
= 25°C V
DD
= 5V, V
SS
= V
EE
= 0V (unless otherwise noted)
Limits
Characteristic
Output Leakage Current
Symbol
I
CEX
Applicable Devices
MIC5841
MIC5842
Collector-Emitter Saturation Voltage
V
CE(SAT)
Both
Test Conditions
V
OUT
= 50V
V
OUT
= 50V, T
A
= +70ºC
V
OUT
= 80V
V
OUT
= 80V, T
A
= +70ºC
I
OUT
= 100mA
I
OUT
= 200mA
I
OUT
= 350mA, V
DD
= 7.0V
I
OUT
= 350mA, L = 2mH
I
OUT
= 350mA, L = 2mH
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V(4)
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V
All Drivers ON, V
DD
= 12V
All Drivers ON, V
DD
= 10V
All Drivers ON, V
DD
= 5.0V
All Drivers OFF, V
DD
= 12V
All Drivers OFF, V
DD
= 10V
All Drivers OFF, V
DD
= 5.0V
V
R
= 50V
V
R
= 80V
I
F
= 350mA
Min
Max
50
100
50
100
1.1
1.3
1.6
35
50
0.8
10.5
8.5
3.5
50
50
50
16
14
8.0
2.9
2.5
1.6
50
50
2.0
Unit
µA
V
Collector-Emitter Saturation Voltage
Input Voltage
V
CE(SUS)(5)
V
IN(0)
V
IN(1)
MIC5841
MIC5842
Both
Both
V
V
Input Resistance
R
IN
Both
kΩ
Supply Current
IDD
(ON)
Both
1.6
IDD
(OFF)
Both
Clamp Diode Leakage Current
Clamp Diode Forward Voltage
I
R
V
F
MIC5841
MIC5842
Both
µA
V
May 2006
3
M9999-050506
(408) 955-1690
Micrel, Inc.
MIC5841/42
Electrical Characteristics
At T
A
= –55°C V
DD
= 5V, V
SS
= V
EE
= 0V (unless otherwise noted)
Limits
Characteristic
Output Leakage Current
Collector-Emitter Saturation Voltage
Symbol
I
CEX
V
CE(SAT)
Test Conditions
V
OUT
= 80V
I
OUT
= 100mA
I
OUT
= 200mA
I
OUT
= 350mA, V
DD
= 7.0V
V
DD
= 12V
V
DD
= 5.0V
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V
All Drivers ON, V
DD
= 12V
All Drivers ON, V
DD
= 10V
All Drivers ON, V
DD
= 5.0V
All Drivers OFF, V
DD
= 12V
All Drivers OFF, V
DD
= 5.0V
10.5
3.5
35
35
35
16
14
10
3.5
2.0
Min
Max
50
1.3
1.5
1.8
0.8
Unit
µA
V
Input Voltage
V
IN(0)
V
IN(1)
R
IN
V
Input Resistance
kΩ
Supply Current
I
DD(ON)
mA
I
DD(OFF)
Electrical Characteristics
At T
A
= +125°C V
DD
= 5V, V
SS
= V
EE
= 0V (unless otherwise noted)
Limits
Characteristic
Output Leakage Current
Collector-Emitter Saturation Voltage
Symbol
I
CEX
V
CE(SAT)
Test Conditions
V
OUT
= 80V
I
OUT
= 100mA
I
OUT
= 200mA
I
OUT
= 350mA, V
DD
= 7.0V
V
DD
= 12V
V
DD
= 5.0V
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V
All Drivers ON, V
DD
= 12V
All Drivers ON, V
DD
= 10V
All Drivers ON, V
DD
= 5.0V
All Drivers OFF, V
DD
= 12V
All Drivers OFF, V
DD
= 5.0V
MIC5841A V
R
= 50V
MIC5842A V
R
= 80V
10.5
3.5
50
50
50
16
14
8
2.9
2.1.6
1.6
100
Min
Max
500
1.3
1.5
1.8
0.8
Unit
µA
V
Input Voltage
V
IN(0)
V
IN(1)
R
IN
V
Input Resistance
kΩ
Supply Current
I
DD(ON)
mA
I
DD(OFF)
Clamp Diode Leakage Current
I
R
µA
Notes:
1. For Inductive load applications.
2. Derate at the rate of 18.2mW/°C above TA = 25°C (Plastic DIP)
3. CMOS devices have input-static protection but are susceptible to damage when exposed to extremely high static electrical charges.
4. Operation of these devices with standard TTL may require the use of appropriate pull-up resistors to insure an input logic HIGH.
5. Not 100% tested. Guaranteed by design.
May 2006
4
M9999-050506
(408) 955-1690
Micrel, Inc.
MIC5841/42
Timing Conditions
(TA = 25°C Logic Levels are V
DD
and V
SS
)
V
DD
= 5V
A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time)...................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................ 75 ns
C. Minimum Data Pulse Width ................................................................................................................................... 150 ns
D. Minimum Clock Pulse Width................................................................................................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ........................................................................................... 300 ns
F. Minimum Strobe Pulse Width.................................................................................................................................. 100 ns
G. Typical Time Between Strobe Activation and Output Transition............................................................................ 500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the ENABLE input be high during serial data entry.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the
latches or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches.
空分复用 (SDM) MIMO 处理可显著提高频谱效率，进而大幅增加无线通信系统的容量。空分复用 MIMO 通信系统作为一种能够大幅提升无线系统容量和连接可靠性的手段，近来吸引了人们的广泛关注。 MIMO 无线系统最佳硬判决检测方式是最大似然 (ML) 检测器。ML 检测因为比特误码率 (BER)性能出众，非常受欢迎。不过，直接实施的复杂性会随着天线和调制方案的增加呈指数级增强，使...[详细]
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